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From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v4 2/9] spapr: move the IRQ server number mapping under the machine
Date: Thu, 30 Mar 2017 17:46:05 +1100	[thread overview]
Message-ID: <20170330064605.GF22163@umbus> (raw)
In-Reply-To: <1490795611-4762-3-git-send-email-clg@kaod.org>

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On Wed, Mar 29, 2017 at 03:53:24PM +0200, Cédric Le Goater wrote:
> This is the second step to abstract the IRQ 'server' number of the
> XICS layer. Now that the prereq cleanups have been done in the
> previous patch, we can move down the 'cpu_dt_id' to 'cpu_index'
> mapping in the sPAPR machine handler.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
>  hw/intc/xics_spapr.c    | 5 ++---
>  hw/ppc/spapr.c          | 3 ++-
>  hw/ppc/spapr_cpu_core.c | 2 +-
>  3 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
> index 58f100d379cb..f05308b897f2 100644
> --- a/hw/intc/xics_spapr.c
> +++ b/hw/intc/xics_spapr.c
> @@ -52,9 +52,8 @@ static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>  static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>                            target_ulong opcode, target_ulong *args)
>  {
> -    target_ulong server = xics_get_cpu_index_by_dt_id(args[0]);
>      target_ulong mfrr = args[1];
> -    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), server);
> +    ICPState *icp = xics_icp_get(XICS_FABRIC(spapr), args[0]);
>  
>      if (!icp) {
>          return H_PARAMETER;
> @@ -122,7 +121,7 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>      }
>  
>      nr = rtas_ld(args, 0);
> -    server = xics_get_cpu_index_by_dt_id(rtas_ld(args, 1));
> +    server = rtas_ld(args, 1);
>      priority = rtas_ld(args, 2);
>  
>      if (!ics_valid_irq(ics, nr) || !xics_icp_get(XICS_FABRIC(spapr), server)
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 8aecea3dd10c..b9f7f8607869 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -3024,9 +3024,10 @@ static void spapr_ics_resend(XICSFabric *dev)
>      ics_resend(spapr->ics);
>  }
>  
> -static ICPState *spapr_icp_get(XICSFabric *xi, int server)
> +static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id)
>  {
>      sPAPRMachineState *spapr = SPAPR_MACHINE(xi);
> +    int server = xics_get_cpu_index_by_dt_id(cpu_dt_id);

The idea is good, but this is a bad name (as it was in the original
version, too).  The whole point here is that the XICS server number
(as it appears in the ICS registers) is the input to this function,
and we no longer assume that is equal to cpu_index.

Seems we could just get the cpu object by dt_id here, then go to ICP(cpu->intc).

>      return (server < spapr->nr_servers) ? &spapr->icps[server] : NULL;
>  }
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index 7db61bd72476..4e1a99591d19 100644
> --- a/hw/ppc/spapr_cpu_core.c
> +++ b/hw/ppc/spapr_cpu_core.c
> @@ -64,7 +64,7 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
>  {
>      CPUPPCState *env = &cpu->env;
>      XICSFabric *xi = XICS_FABRIC(spapr);
> -    ICPState *icp = xics_icp_get(xi, CPU(cpu)->cpu_index);
> +    ICPState *icp = xics_icp_get(xi, cpu->cpu_dt_id);
>  
>      /* Set time-base frequency to 512 MHz */
>      cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2017-03-30 11:01 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-29 13:53 [Qemu-devel] [PATCH v4 0/9] ppc/pnv: interrupt controller (POWER8) Cédric Le Goater
2017-03-29 13:53 ` [Qemu-devel] [PATCH v4 1/9] ppc/xics: introduce an 'intc' backlink under PowerPCCPU Cédric Le Goater
2017-03-30  6:46   ` David Gibson
2017-03-29 13:53 ` [Qemu-devel] [PATCH v4 2/9] spapr: move the IRQ server number mapping under the machine Cédric Le Goater
2017-03-30  6:46   ` David Gibson [this message]
2017-03-30 13:04     ` Cédric Le Goater
2017-03-30 15:04       ` Cedric Le Goater
2017-04-02  6:48       ` David Gibson
2017-03-30 15:08   ` [Qemu-devel] [PATCH v4 2+/9] spapr: allocate the ICPState object from under sPAPRCPUCore Cédric Le Goater
2017-03-30 15:56     ` Cédric Le Goater
2017-04-02  8:25     ` David Gibson
2017-04-02 17:16       ` Cédric Le Goater
2017-03-29 13:53 ` [Qemu-devel] [PATCH v4 3/9] ppc/xics: add a realize() handler to ICPStateClass Cédric Le Goater
2017-03-29 13:53 ` [Qemu-devel] [PATCH v4 4/9] ppc/pnv: add a PnvICPState object Cédric Le Goater
2017-03-29 13:53 ` [Qemu-devel] [PATCH v4 5/9] ppc/pnv: create the ICP object under PnvCore Cédric Le Goater
2017-03-30  8:28   ` [Qemu-devel] [PATCH v4.1 " Cédric Le Goater
2017-04-03  2:18     ` David Gibson
2017-03-29 13:53 ` [Qemu-devel] [PATCH v4 6/9] ppc/pnv: add a helper to calculate MMIO addresses registers Cédric Le Goater
2017-03-29 13:53 ` [Qemu-devel] [PATCH v4 7/9] ppc/pnv: extend the machine with a XICSFabric interface Cédric Le Goater
2017-04-03  2:22   ` David Gibson
2017-03-29 13:53 ` [Qemu-devel] [PATCH v4 8/9] ppc/pnv: extend the machine with a InterruptStatsProvider interface Cédric Le Goater
2017-03-29 13:53 ` [Qemu-devel] [PATCH v4 9/9] ppc/pnv: add memory regions for the ICP registers Cédric Le Goater

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