From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: Date: Thu, 30 Mar 2017 17:19:31 +0100 From: Will Deacon To: Lorenzo Pieralisi Subject: Re: [PATCH v2 05/22] ARM64: implement ioremap_nopost() interface Message-ID: <20170330161931.GA5623@arm.com> References: <20170327094954.7162-1-lorenzo.pieralisi@arm.com> <20170327094954.7162-6-lorenzo.pieralisi@arm.com> MIME-Version: 1.0 In-Reply-To: <20170327094954.7162-6-lorenzo.pieralisi@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Wenrui Li , Gabriele Paoloni , linux-pci@vger.kernel.org, Shawn Lin , Michal Simek , Thierry Reding , Tanmay Inamdar , Joao Pinto , Pratyush Anand , Russell King , Bharat Kumar Gogada , Murali Karicheri , Catalin Marinas , Arnd Bergmann , Jon Mason , Ray Jui , John Garry , Bjorn Helgaas , Mingkai Hu , linux-arm-kernel@lists.infradead.org, "Luis R. Rodriguez" , Thomas Petazzoni , Jingoo Han , linux-kernel@vger.kernel.org, Stanimir Varbanov , Minghuan Lian , Zhou Wang , Roy Zang Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: On Mon, Mar 27, 2017 at 10:49:33AM +0100, Lorenzo Pieralisi wrote: > The PCI bus specifications (rev 3.0, 3.2.5 "Transaction Ordering > and Posting") defines rules for PCI configuration space transactions > ordering and posting, that state that configuration writes > are non-posted transactions. > > This rule is reinforced by the ARM v8 architecture reference manual > (issue A.k, Early Write Acknowledgment) that explicitly recommends > that No Early Write Acknowledgment attribute should be used to map > PCI configuration (write) transactions. > > Current ioremap interface on ARM64 implements mapping functions > where the Early Write Acknowledgment hint is enabled, so they > cannot be used to map PCI configuration space in a PCI specs > compliant way. > > Implement an ARM64 specific ioremap_nopost() interface > that allows to map PCI config region with nGnRnE attributes, providing > a remap function that complies with PCI specifications and the ARMv8 > architecture reference manual recommendations. > > Signed-off-by: Lorenzo Pieralisi > Cc: Will Deacon > Cc: Catalin Marinas > --- > arch/arm64/include/asm/io.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) Acked-by: Will Deacon Let me know if you need this taken via the arm64 tree. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Thu, 30 Mar 2017 17:19:31 +0100 Subject: [PATCH v2 05/22] ARM64: implement ioremap_nopost() interface In-Reply-To: <20170327094954.7162-6-lorenzo.pieralisi@arm.com> References: <20170327094954.7162-1-lorenzo.pieralisi@arm.com> <20170327094954.7162-6-lorenzo.pieralisi@arm.com> Message-ID: <20170330161931.GA5623@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Mar 27, 2017 at 10:49:33AM +0100, Lorenzo Pieralisi wrote: > The PCI bus specifications (rev 3.0, 3.2.5 "Transaction Ordering > and Posting") defines rules for PCI configuration space transactions > ordering and posting, that state that configuration writes > are non-posted transactions. > > This rule is reinforced by the ARM v8 architecture reference manual > (issue A.k, Early Write Acknowledgment) that explicitly recommends > that No Early Write Acknowledgment attribute should be used to map > PCI configuration (write) transactions. > > Current ioremap interface on ARM64 implements mapping functions > where the Early Write Acknowledgment hint is enabled, so they > cannot be used to map PCI configuration space in a PCI specs > compliant way. > > Implement an ARM64 specific ioremap_nopost() interface > that allows to map PCI config region with nGnRnE attributes, providing > a remap function that complies with PCI specifications and the ARMv8 > architecture reference manual recommendations. > > Signed-off-by: Lorenzo Pieralisi > Cc: Will Deacon > Cc: Catalin Marinas > --- > arch/arm64/include/asm/io.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) Acked-by: Will Deacon Let me know if you need this taken via the arm64 tree. Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934486AbdC3QTT (ORCPT ); Thu, 30 Mar 2017 12:19:19 -0400 Received: from foss.arm.com ([217.140.101.70]:49614 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934295AbdC3QTR (ORCPT ); Thu, 30 Mar 2017 12:19:17 -0400 Date: Thu, 30 Mar 2017 17:19:31 +0100 From: Will Deacon To: Lorenzo Pieralisi Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Catalin Marinas , Arnd Bergmann , Russell King , Pratyush Anand , Jingoo Han , Bjorn Helgaas , Mingkai Hu , John Garry , Tanmay Inamdar , Murali Karicheri , Bharat Kumar Gogada , Ray Jui , Wenrui Li , Shawn Lin , Minghuan Lian , Jon Mason , Gabriele Paoloni , Thomas Petazzoni , Joao Pinto , Thierry Reding , Michal Simek , Stanimir Varbanov , Zhou Wang , Roy Zang , "Luis R. Rodriguez" Subject: Re: [PATCH v2 05/22] ARM64: implement ioremap_nopost() interface Message-ID: <20170330161931.GA5623@arm.com> References: <20170327094954.7162-1-lorenzo.pieralisi@arm.com> <20170327094954.7162-6-lorenzo.pieralisi@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170327094954.7162-6-lorenzo.pieralisi@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 27, 2017 at 10:49:33AM +0100, Lorenzo Pieralisi wrote: > The PCI bus specifications (rev 3.0, 3.2.5 "Transaction Ordering > and Posting") defines rules for PCI configuration space transactions > ordering and posting, that state that configuration writes > are non-posted transactions. > > This rule is reinforced by the ARM v8 architecture reference manual > (issue A.k, Early Write Acknowledgment) that explicitly recommends > that No Early Write Acknowledgment attribute should be used to map > PCI configuration (write) transactions. > > Current ioremap interface on ARM64 implements mapping functions > where the Early Write Acknowledgment hint is enabled, so they > cannot be used to map PCI configuration space in a PCI specs > compliant way. > > Implement an ARM64 specific ioremap_nopost() interface > that allows to map PCI config region with nGnRnE attributes, providing > a remap function that complies with PCI specifications and the ARMv8 > architecture reference manual recommendations. > > Signed-off-by: Lorenzo Pieralisi > Cc: Will Deacon > Cc: Catalin Marinas > --- > arch/arm64/include/asm/io.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) Acked-by: Will Deacon Let me know if you need this taken via the arm64 tree. Will