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From: Yi Sun <yi.y.sun@linux.intel.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
	he.chen@linux.intel.com, andrew.cooper3@citrix.com,
	dario.faggioli@citrix.com, ian.jackson@eu.citrix.com,
	mengxu@cis.upenn.edu, xen-devel@lists.xenproject.org,
	chao.p.peng@linux.intel.com, roger.pau@citrix.com
Subject: Re: [PATCH v9 12/25] x86: refactor psr: L3 CAT: set value: implement cos id picking flow.
Date: Fri, 31 Mar 2017 21:22:20 +0800	[thread overview]
Message-ID: <20170331132220.GD17458@yi.y.sun> (raw)
In-Reply-To: <58DE6CDB020000780014B4E8@prv-mh.provo.novell.com>

On 17-03-31 06:51:07, Jan Beulich wrote:
> >>> On 31.03.17 at 14:40, <yi.y.sun@linux.intel.com> wrote:
> > On 17-03-31 04:19:49, Jan Beulich wrote:
> >> >>> On 31.03.17 at 11:12, <yi.y.sun@linux.intel.com> wrote:
> >> > On 17-03-31 02:47:25, Jan Beulich wrote:
> >> >> >>> On 30.03.17 at 14:10, <yi.y.sun@linux.intel.com> wrote:
> >> >> > I think you can check v9 codes here:
> >> >> > https://github.com/yisun-git/xen/tree/l2_cat_v9 
> >> >> 
> >> >> Looking at this made me notice that cat_get_old_val() passes a
> >> >> bogus literal 0 to cat_get_val(), which needs taking care of too.
> >> >> One option I can see is for each feature to make available an
> >> >> array of type enum cbm_type, with cos_num elements. The order
> >> >> would match that of the order of values in their arrays. This will
> >> > 
> >> > Sorry, not very clear your meaning. How to do that? Could you please
> >> > provide pieces of codes? Thanks!
> >> 
> >> I'm sorry, but I'm afraid I don't see how I would reasonably supply
> >> code here without taking over your series altogether (which I don't
> >> intend to do). What is unclear with, at the example of CDP, you
> >> needing to add an array at initialization time, slot 0 of which holds
> >> PSR_CBM_TYPE_L3_DATA and slot 1 PSR_CBM_TYPE_L3_CODE (or
> >> the other way around). Granted I was wrong with the type of the
> >> array (as the above aren't enum psr_feat_type enumerators, but
> >> enum cbm_type ones), but I think the basic idea should have been
> >> clear anyway: You need to provide a way for generic code to pass
> >> suitable type information into ->get_val().
> >> 
> > May I change the 'get_val()' parameter 'enum cbm_type' to a generic type
> > 'unsigned int' to make it be a flexible type,  and then combine feature
> > type with cos_num together as a flag to indicate which feature it is,
> > which value to get and distinguish it with cbm_type? For example:
> > 
> > #define CDP_GATHER_BOTH_DATA ( PSR_SOCKET_L3_CDP << 16 )
> > #define CDP_GATHER_BOTH_CODE ( PSR_SOCKET_L3_CDP << 16 + 1 )
> > static void l3_cdp_get_val(const struct feat_node *feat, unsigned int cos,
> >                            unsigned int type, uint32_t *val)
> > {
> >     switch ( type )
> >     {
> >     case PSR_CBM_TYPE_L3_DATA:
> >     case CDP_GATHER_BOTH_DATA:
> >         *val = get_cdp_data(feat, cos);
> >         break;
> >     case PSR_CBM_TYPE_L3_CODE:
> >     case CDP_GATHER_BOTH_CODE:
> >         *val = get_cdp_code(feat, cos);
> >         break;
> >     }
> > }
> 
> The two case labels are still indicative of unnecessary redundancy
> (and, even right now only highly theoretical, risk of collisions). What's
> wrong with the model I've proposed?
> 
Oh, sorry. I did not understand your proposal just now so I provided another
solution.

After reading your suggestion again, I think your meaing is below in codes:

struct feat_props {
...
    unsigned int cos_num;
    enum cbm_type cos_to_type[2];
...
}

static void cat_init_feature(...)
{
...
    case PSR_SOCKET_L3_CDP:
        feat->props->cos_to_type[0] = PSR_CBM_TYPE_L3_DATA;
        feat->props->cos_to_type[1] = PSR_CBM_TYPE_L3_CODE;
...
}

Then, in functions to iterate 'cos_num', we can input 'cos_to_type[i]'. Right?

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  reply	other threads:[~2017-03-31 13:21 UTC|newest]

Thread overview: 105+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-16 11:07 [PATCH v9 00/25] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-03-16 11:07 ` [PATCH v9 01/25] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document Yi Sun
2017-03-16 11:07 ` [PATCH v9 02/25] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-03-16 11:07 ` [PATCH v9 03/25] x86: refactor psr: implement main data structures Yi Sun
2017-03-24 16:19   ` Jan Beulich
2017-03-27  2:38     ` Yi Sun
2017-03-27  6:20       ` Jan Beulich
2017-03-27  7:12         ` Yi Sun
2017-03-27  7:37           ` Jan Beulich
2017-03-16 11:07 ` [PATCH v9 04/25] x86: move cpuid_count_leaf from cpuid.c to processor.h Yi Sun
2017-03-24 16:22   ` Jan Beulich
2017-03-16 11:07 ` [PATCH v9 05/25] x86: refactor psr: L3 CAT: implement CPU init and free flow Yi Sun
2017-03-24 16:52   ` Jan Beulich
2017-03-27  4:41     ` Yi Sun
2017-03-27  6:34       ` Jan Beulich
2017-03-27  8:16         ` Yi Sun
2017-03-27  8:43           ` Jan Beulich
2017-03-16 11:07 ` [PATCH v9 06/25] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows Yi Sun
2017-03-16 11:07 ` [PATCH v9 07/25] x86: refactor psr: L3 CAT: implement get hw info flow Yi Sun
2017-03-27  9:07   ` Jan Beulich
2017-03-27 12:24     ` Yi Sun
2017-03-27 12:51       ` Jan Beulich
2017-03-27 13:19         ` Yi Sun
2017-03-27 13:32           ` Jan Beulich
2017-03-16 11:07 ` [PATCH v9 08/25] x86: refactor psr: L3 CAT: implement get value flow Yi Sun
2017-03-27  9:23   ` Jan Beulich
2017-03-27 12:59     ` Yi Sun
2017-03-27 13:34       ` Jan Beulich
2017-03-28  2:13         ` Yi Sun
2017-03-28  8:10           ` Jan Beulich
2017-03-16 11:07 ` [PATCH v9 09/25] x86: refactor psr: L3 CAT: set value: implement framework Yi Sun
2017-03-27  9:59   ` Jan Beulich
2017-03-28  1:21     ` Yi Sun
2017-03-28  8:21       ` Jan Beulich
2017-03-16 11:08 ` [PATCH v9 10/25] x86: refactor psr: L3 CAT: set value: assemble features value array Yi Sun
2017-03-27 10:17   ` Jan Beulich
2017-03-28  3:12     ` Yi Sun
2017-03-28  8:05       ` Yi Sun
2017-03-28  8:36         ` Jan Beulich
2017-03-28  9:11           ` Yi Sun
2017-03-28  9:20             ` Jan Beulich
2017-03-28 10:18               ` Yi Sun
2017-03-28 10:39                 ` Jan Beulich
2017-03-28  8:34       ` Jan Beulich
2017-03-28 10:12         ` Yi Sun
2017-03-28 10:36           ` Jan Beulich
2017-03-16 11:08 ` [PATCH v9 11/25] x86: refactor psr: L3 CAT: set value: implement cos finding flow Yi Sun
2017-03-27 10:28   ` Jan Beulich
2017-03-28  3:26     ` Yi Sun
2017-03-28  8:41       ` Jan Beulich
2017-03-16 11:08 ` [PATCH v9 12/25] x86: refactor psr: L3 CAT: set value: implement cos id picking flow Yi Sun
2017-03-27 10:37   ` Jan Beulich
2017-03-28  4:58     ` Yi Sun
2017-03-28  8:45       ` Jan Beulich
2017-03-28 10:31         ` Yi Sun
2017-03-28 10:40           ` Jan Beulich
2017-03-28 11:59             ` Yi Sun
2017-03-28 12:20               ` Jan Beulich
2017-03-29  1:20                 ` Yi Sun
2017-03-29  1:36                   ` Yi Sun
2017-03-29  9:57                     ` Jan Beulich
2017-03-30  1:37                       ` Yi Sun
2017-03-30  1:39                         ` Yi Sun
2017-03-30 11:55                         ` Jan Beulich
2017-03-30 12:10                           ` Yi Sun
2017-03-31  8:47                             ` Jan Beulich
2017-03-31  9:12                               ` Yi Sun
2017-03-31  9:18                                 ` Yi Sun
2017-03-31 10:19                                 ` Jan Beulich
2017-03-31 12:40                                   ` Yi Sun
2017-03-31 12:51                                     ` Jan Beulich
2017-03-31 13:22                                       ` Yi Sun [this message]
2017-03-31 14:35                                         ` Jan Beulich
2017-03-31 14:46                                           ` Yi Sun
2017-03-16 11:08 ` [PATCH v9 13/25] x86: refactor psr: L3 CAT: set value: implement write msr flow Yi Sun
2017-03-27 10:46   ` Jan Beulich
2017-03-28  5:06     ` Yi Sun
2017-03-28  8:48       ` Jan Beulich
2017-03-28 10:20         ` Yi Sun
2017-03-16 11:08 ` [PATCH v9 14/25] x86: refactor psr: CDP: implement CPU init and free flow Yi Sun
2017-03-27 13:58   ` Jan Beulich
2017-03-16 11:08 ` [PATCH v9 15/25] x86: refactor psr: CDP: implement get hw info flow Yi Sun
2017-03-27 14:08   ` Jan Beulich
2017-03-28  5:13     ` Yi Sun
2017-03-16 11:08 ` [PATCH v9 16/25] x86: refactor psr: CDP: implement get value flow Yi Sun
2017-03-16 11:08 ` [PATCH v9 17/25] x86: refactor psr: CDP: implement set value callback functions Yi Sun
2017-03-27 14:17   ` Jan Beulich
2017-03-28  5:14     ` Yi Sun
2017-03-16 11:08 ` [PATCH v9 18/25] x86: L2 CAT: implement CPU init and free flow Yi Sun
2017-03-16 11:08 ` [PATCH v9 19/25] x86: L2 CAT: implement get hw info flow Yi Sun
2017-03-27 14:38   ` Jan Beulich
2017-03-28  5:16     ` Yi Sun
2017-03-16 11:08 ` [PATCH v9 20/25] x86: L2 CAT: implement get value flow Yi Sun
2017-03-27 14:39   ` Jan Beulich
2017-03-16 11:08 ` [PATCH v9 21/25] x86: L2 CAT: implement set " Yi Sun
2017-03-27 14:40   ` Jan Beulich
2017-03-16 11:08 ` [PATCH v9 22/25] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-03-16 11:08 ` [PATCH v9 23/25] tools: L2 CAT: support show cbm " Yi Sun
2017-03-16 11:08 ` [PATCH v9 24/25] tools: L2 CAT: support set " Yi Sun
2017-03-28 14:04   ` Wei Liu
2017-03-29  1:21     ` Yi Sun
2017-03-16 11:08 ` [PATCH v9 25/25] docs: add L2 CAT description in docs Yi Sun
2017-03-16 11:20 ` [PATCH v9 00/25] Enable L2 Cache Allocation Technology & Refactor psr.c Jan Beulich
2017-03-17  1:29   ` Yi Sun
2017-03-17  7:25     ` Jan Beulich

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