From: Dan Carpenter <dan.carpenter-QHcLZuEGTsvQT0dZR+AlfA@public.gmane.org>
To: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Ken Wang <Qingqing.Wang-5C7GfCeVMHo@public.gmane.org>,
amd-gfx list
<amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [bug report] drm/amdgpu: soc15 enable (v3)
Date: Mon, 3 Apr 2017 22:29:19 +0300 [thread overview]
Message-ID: <20170403192919.GB4470@mwanda> (raw)
In-Reply-To: <CADnq5_OUXQUFG7kvg_FuLd+Pz0wy9q3gFEe68cm6C7ozpbaZzg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Mon, Apr 03, 2017 at 03:12:31PM -0400, Alex Deucher wrote:
> On Mon, Apr 3, 2017 at 2:53 PM, Dan Carpenter <dan.carpenter@oracle.com> wrote:
> > Hello Ken Wang,
> >
> > The patch 220ab9bd1ccf: "drm/amdgpu: soc15 enable (v3)" from Mar 6,
> > 2017, leads to the following static checker warning:
> >
> > drivers/gpu/drm/amd/amdgpu/soc15.c:110 soc15_pcie_rreg()
> > error: potentially dereferencing uninitialized 'nbio_pcie_id'.
> >
> > drivers/gpu/drm/amd/amdgpu/soc15.c
> > 101 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
> > 102 {
> > 103 unsigned long flags, address, data;
> > 104 u32 r;
> > 105 struct nbio_pcie_index_data *nbio_pcie_id;
> > 106
> > 107 if (adev->asic_type == CHIP_VEGA10)
> > 108 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
> >
> > There should be an else statement to this probably?
>
> Currently vega10 is the only soc15 gpu so there is else case yet.
>
Yeah. I figured. But it's annoying to have half implemented code and
static checker warnings.
regards,
dan carpenter
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next prev parent reply other threads:[~2017-04-03 19:29 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-03 18:53 [bug report] drm/amdgpu: soc15 enable (v3) Dan Carpenter
2017-04-03 19:12 ` Alex Deucher
[not found] ` <CADnq5_OUXQUFG7kvg_FuLd+Pz0wy9q3gFEe68cm6C7ozpbaZzg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-04-03 19:29 ` Dan Carpenter [this message]
2017-04-03 19:35 ` Dan Carpenter
2017-04-03 19:54 ` Deucher, Alexander
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