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From: Manasi Navare <manasi.d.navare@intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dhinakaran.pandiyan@intel.com
Subject: Re: [PATCH v3 04/14] drm/i915/dp: cache source rates at init
Date: Tue, 4 Apr 2017 18:17:07 -0700	[thread overview]
Message-ID: <20170405011707.GE2688@intel.com> (raw)
In-Reply-To: <aa998882d2b824f671272c60e9d26621ab9d2d17.1490712890.git.jani.nikula@intel.com>


Reviewed-by: <manasi.d.navare@intel.com>

Manasi

On Tue, Mar 28, 2017 at 05:59:04PM +0300, Jani Nikula wrote:
> We need the source rates array so often that it makes sense to set it
> once at init. This reduces function calls when we need the rates, making
> the code easier to follow.
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c  | 35 +++++++++++++++++++++--------------
>  drivers/gpu/drm/i915/intel_drv.h |  3 +++
>  2 files changed, 24 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9fc066dda4e0..e9bd75ff3904 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -218,21 +218,25 @@ intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
>  	return (intel_dp->max_sink_link_bw >> 3) + 1;
>  }
>  
> -static int
> -intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
> +static void
> +intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> +	const int *source_rates;
>  	int size;
>  
> +	/* This should only be done once */
> +	WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
> +
>  	if (IS_GEN9_LP(dev_priv)) {
> -		*source_rates = bxt_rates;
> +		source_rates = bxt_rates;
>  		size = ARRAY_SIZE(bxt_rates);
>  	} else if (IS_GEN9_BC(dev_priv)) {
> -		*source_rates = skl_rates;
> +		source_rates = skl_rates;
>  		size = ARRAY_SIZE(skl_rates);
>  	} else {
> -		*source_rates = default_rates;
> +		source_rates = default_rates;
>  		size = ARRAY_SIZE(default_rates);
>  	}
>  
> @@ -240,7 +244,8 @@ intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
>  	if (!intel_dp_source_supports_hbr2(intel_dp))
>  		size--;
>  
> -	return size;
> +	intel_dp->source_rates = source_rates;
> +	intel_dp->num_source_rates = size;
>  }
>  
>  static int intersect_rates(const int *source_rates, int source_len,
> @@ -281,13 +286,13 @@ static int intel_dp_rate_index(const int *rates, int len, int rate)
>  static int intel_dp_common_rates(struct intel_dp *intel_dp,
>  				 int *common_rates)
>  {
> -	const int *source_rates, *sink_rates;
> -	int source_len, sink_len;
> +	const int *sink_rates;
> +	int sink_len;
>  
>  	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
> -	source_len = intel_dp_source_rates(intel_dp, &source_rates);
>  
> -	return intersect_rates(source_rates, source_len,
> +	return intersect_rates(intel_dp->source_rates,
> +			       intel_dp->num_source_rates,
>  			       sink_rates, sink_len,
>  			       common_rates);
>  }
> @@ -1493,16 +1498,16 @@ static void snprintf_int_array(char *str, size_t len,
>  
>  static void intel_dp_print_rates(struct intel_dp *intel_dp)
>  {
> -	const int *source_rates, *sink_rates;
> -	int source_len, sink_len, common_len;
> +	const int *sink_rates;
> +	int sink_len, common_len;
>  	int common_rates[DP_MAX_SUPPORTED_RATES];
>  	char str[128]; /* FIXME: too big for stack? */
>  
>  	if ((drm_debug & DRM_UT_KMS) == 0)
>  		return;
>  
> -	source_len = intel_dp_source_rates(intel_dp, &source_rates);
> -	snprintf_int_array(str, sizeof(str), source_rates, source_len);
> +	snprintf_int_array(str, sizeof(str),
> +			   intel_dp->source_rates, intel_dp->num_source_rates);
>  	DRM_DEBUG_KMS("source rates: %s\n", str);
>  
>  	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
> @@ -5943,6 +5948,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  		 intel_dig_port->max_lanes, port_name(port)))
>  		return false;
>  
> +	intel_dp_set_source_rates(intel_dp);
> +
>  	intel_dp->reset_link_params = true;
>  	intel_dp->pps_pipe = INVALID_PIPE;
>  	intel_dp->active_pipe = INVALID_PIPE;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e24641b559e2..f59574261dc6 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -949,6 +949,9 @@ struct intel_dp {
>  	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>  	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
>  	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> +	/* source rates */
> +	int num_source_rates;
> +	const int *source_rates;
>  	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
>  	uint8_t num_sink_rates;
>  	int sink_rates[DP_MAX_SUPPORTED_RATES];
> -- 
> 2.1.4
> 
_______________________________________________
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  reply	other threads:[~2017-04-05  1:13 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-28 14:59 [PATCH v3 00/14] drm/i915/dp: link rate and lane count refactoring Jani Nikula
2017-03-28 14:59 ` [PATCH v3 01/14] drm/i915/dp: use known correct array size in rate_to_index Jani Nikula
2017-04-04 19:16   ` Manasi Navare
2017-03-28 14:59 ` [PATCH v3 02/14] drm/i915/dp: return errors from rate_to_index() Jani Nikula
2017-03-28 19:16   ` Manasi Navare
2017-03-29  7:17     ` Jani Nikula
2017-04-04 19:17       ` Manasi Navare
2017-03-28 14:59 ` [PATCH v3 03/14] drm/i915/dp: rename rate_to_index() to intel_dp_rate_index() and reuse Jani Nikula
2017-04-04 19:19   ` Manasi Navare
2017-03-28 14:59 ` [PATCH v3 04/14] drm/i915/dp: cache source rates at init Jani Nikula
2017-04-05  1:17   ` Manasi Navare [this message]
2017-03-28 14:59 ` [PATCH v3 05/14] drm/i915/dp: generate and cache sink rate array for all DP, not just eDP 1.4 Jani Nikula
2017-04-05  1:20   ` Manasi Navare
2017-04-06 11:41     ` Jani Nikula
2017-03-28 14:59 ` [PATCH v3 06/14] drm/i915/dp: use the sink rates array for max sink rates Jani Nikula
2017-03-28 14:59 ` [PATCH v3 07/14] drm/i915/dp: cache common rates with " Jani Nikula
2017-04-05  1:21   ` Manasi Navare
2017-03-28 14:59 ` [PATCH v3 08/14] drm/i915/dp: do not limit rate seek when not needed Jani Nikula
2017-03-28 21:02   ` Manasi Navare
2017-03-29  9:23   ` [PATCH] " Jani Nikula
2017-04-05  1:24     ` Manasi Navare
2017-03-28 14:59 ` [PATCH v3 09/14] drm/i915/dp: don't call the link parameters sink parameters Jani Nikula
2017-03-28 21:11   ` Manasi Navare
2017-03-28 14:59 ` [PATCH v3 10/14] drm/i915/dp: add functions for max common link rate and lane count Jani Nikula
2017-03-28 21:47   ` Manasi Navare
2017-03-28 14:59 ` [PATCH v3 11/14] drm/i915/mst: use max link not sink " Jani Nikula
2017-03-28 21:51   ` Manasi Navare
2017-03-28 14:59 ` [PATCH v3 12/14] drm/i915/dp: localize link rate index variable more Jani Nikula
2017-03-28 22:00   ` Manasi Navare
2017-03-29  7:22     ` Jani Nikula
2017-04-05  1:26       ` Manasi Navare
2017-03-28 14:59 ` [PATCH v3 13/14] drm/i915/dp: use readb and writeb calls for single byte DPCD access Jani Nikula
2017-04-05  1:28   ` Manasi Navare
2017-03-28 14:59 ` [PATCH v3 14/14] drm/i915/dp: read sink count to a temporary variable first Jani Nikula
2017-03-28 16:50 ` ✓ Fi.CI.BAT: success for drm/i915/dp: link rate and lane count refactoring (rev3) Patchwork
2017-03-29  9:48 ` ✓ Fi.CI.BAT: success for drm/i915/dp: link rate and lane count refactoring (rev4) Patchwork

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