From: keith.busch@intel.com (Keith Busch)
Subject: PRP1 not min page size aligned in read/write cmds
Date: Wed, 5 Apr 2017 09:12:25 -0400 [thread overview]
Message-ID: <20170405131225.GR20181@localhost.localdomain> (raw)
In-Reply-To: <CAG3=cOn1rZHQ7dETovf5n=_3QRSMOrZFC+PibNJiQeH0kr2ZWA@mail.gmail.com>
On Tue, Apr 04, 2017@06:28:30PM -0700, Nisha Miller wrote:
> We have specified Min page size as 4K in our FW. So we expect that all
> read/write commands sent to FW will operate on multiples of 4K blocks.
> However we observe that sometimes we receive read/write commands where
> the PRP1 address is not 4K aligned, e.g 0x84CD5CD50. Is this normal or
> expected?
Yes, the first PRP entry and any list pointer may have an offset. The
remaining entries can not. See section 4.3, figure 14 in NVMe 1.2.1 spec.
prev parent reply other threads:[~2017-04-05 13:12 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-05 1:28 PRP1 not min page size aligned in read/write cmds Nisha Miller
2017-04-05 13:12 ` Keith Busch [this message]
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