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From: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Tom St Denis <tom.stdenis-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 01/10] drm/amd/amdgpu: cleanup gfx_v9_0_init_queue()
Date: Wed, 5 Apr 2017 09:26:01 -0400	[thread overview]
Message-ID: <20170405132610.26075-1-tom.stdenis@amd.com> (raw)

Introduce WREG32_FIELD15 macro for SOC15 architectures.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  3 +++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++--------
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d0a3987b221a..04c84332cc58 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1719,6 +1719,9 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
 #define WREG32_FIELD_OFFSET(reg, offset, field, val)	\
 	WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
 
+#define WREG32_FIELD15(ip, idx, reg, field, val)	\
+	WREG32(SOC15_REG_OFFSET(ip, idx, mm##reg), (RREG32(SOC15_REG_OFFSET(ip, idx, mm##reg)) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
+
 /*
  * BIOS helpers.
  */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index a967879524bc..3888743bc868 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3975,9 +3975,7 @@ static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
 			       ring->pipe,
 			       ring->queue, 0);
 	/* disable wptr polling */
-	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL));
-	tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL), tmp);
+	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
 
 	/* write the EOP addr */
 	BUG_ON(ring->me != 1 || ring->pipe != 0); /* can't handle other cases eop address */
@@ -4121,11 +4119,8 @@ static int gfx_v9_0_init_queue(struct amdgpu_ring *ring)
 	amdgpu_bo_kunmap(ring->mqd_obj);
 	amdgpu_bo_unreserve(ring->mqd_obj);
 
-	if (use_doorbell) {
-		tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS));
-		tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_STATUS), tmp);
-	}
+	if (use_doorbell)
+		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
 
 	return 0;
 }
-- 
2.12.0

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             reply	other threads:[~2017-04-05 13:26 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-05 13:26 Tom St Denis [this message]
     [not found] ` <20170405132610.26075-1-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2017-04-05 13:26   ` [PATCH 02/10] drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_inst_fault_state() Tom St Denis
2017-04-05 13:26   ` [PATCH 03/10] drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_reg_fault_state() Tom St Denis
2017-04-05 13:26   ` [PATCH 04/10] drm/amd/amdgpu: cleanup gfx_v9_0_set_gfx_eop_interrupt_state() Tom St Denis
2017-04-05 13:26   ` [PATCH 05/10] drm/amd/amdgpu: Drop gfx_v9_0_print_status() Tom St Denis
2017-04-05 13:26   ` [PATCH 06/10] drm/amd/amdgpu: cleanup gfx_v9_0_kiq_init_register() Tom St Denis
2017-04-05 13:26   ` [PATCH 07/10] drm/amd/amdgpu: simplify gfx_v9_0_cp_gfx_enable() Tom St Denis
2017-04-05 13:26   ` [PATCH 08/10] drm/amd/amdgpu: cleanup gfx_v9_0_rlc_start() Tom St Denis
2017-04-05 13:26   ` [PATCH 09/10] drm/amd/amdgpu: cleanup gfx_v9_0_rlc_reset() Tom St Denis
2017-04-05 13:26   ` [PATCH 10/10] drm/amd/amdgpu: cleanup gfx_v9_0_gpu_init() Tom St Denis
     [not found]     ` <20170405132610.26075-10-tom.stdenis-5C7GfCeVMHo@public.gmane.org>
2017-04-05 18:08       ` Alex Deucher
2017-04-05 14:15   ` [PATCH 01/10] drm/amd/amdgpu: cleanup gfx_v9_0_init_queue() Christian König
     [not found]     ` <a78ee9e1-11eb-7702-ad13-188d9827cf0b-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-05 16:28       ` Tom St Denis

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