diff for duplicates of <20170407093811.GA17455@leoy-linaro> diff --git a/a/1.txt b/N1/1.txt index 1332fad..89ac59c 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -5,8 +5,8 @@ Hi Pengcheng, On Fri, Apr 07, 2017 at 04:06:58PM +0800, Li Pengcheng wrote: > Add coresight DT nodes for hikey board. > -> Signed-off-by: Li Pengcheng <lipengcheng8@huawei.com> -> Signed-off-by: Li Zhong <lizhong11@hisilicon.com> +> Signed-off-by: Li Pengcheng <lipengcheng8-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> +> Signed-off-by: Li Zhong <lizhong11-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> > --- > .../arm64/boot/dts/hisilicon/hi6220-coresight.dtsi | 318 +++++++++++++++++++++ > arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 1 + @@ -23,7 +23,7 @@ On Fri, Apr 07, 2017 at 04:06:58PM +0800, Li Pengcheng wrote: > + * Hisilicon Ltd. Hi6220 SoC > + * > + * Copyright (C) 2015-2016 Hisilicon Ltd. -> + * Author: lipengcheng <lipengcheng8@huawei.com> +> + * Author: lipengcheng <lipengcheng8-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as @@ -56,9 +56,9 @@ I think "#address-cells" and "#size-cells" also can remove. This is defined by its parent node. > + ranges; -> + etm at 0,f659c000 { +> + etm@0,f659c000 { -Change to etm at f659c000? +Change to etm@f659c000? > + compatible = "arm,coresight-etm4x","arm,primecell"; > + reg = <0 0xf659c000 0 0x1000>; @@ -73,7 +73,7 @@ Change to etm at f659c000? > + }; > + }; > + -> + etm at 1,f659d000 { +> + etm@1,f659d000 { Same with above. @@ -91,7 +91,7 @@ Same with above. > + > + }; > + -> + etm at 2,f659e000 { +> + etm@2,f659e000 { Same with above. @@ -108,7 +108,7 @@ Same with above. > + }; > + }; > + -> + etm at 3,f659f000 { +> + etm@3,f659f000 { Same with above. @@ -126,7 +126,7 @@ Same with above. > + }; > + > + /* A53 cluster1 internal coresight */ -> + etm at 4,f65dc000 { +> + etm@4,f65dc000 { Same with above. @@ -146,7 +146,7 @@ Wrong indent. > + }; > + }; > + -> + etm at 5,f65dd000 { +> + etm@5,f65dd000 { Same with above. @@ -166,9 +166,9 @@ Wrong indent. > + }; > + }; > + -> + etm at 6,f65de000 { +> + etm@6,f65de000 { -Change to etm at f65de000? +Change to etm@f65de000? > + compatible = "arm,coresight-etm4x","arm,primecell"; > + reg = <0 0xf65de000 0 0x1000>; @@ -183,7 +183,7 @@ Change to etm at f65de000? > + }; > + }; > + -> + etm at 7,f65df000 { +> + etm@7,f65df000 { Same with above. @@ -200,9 +200,9 @@ Same with above. > + }; > + }; > + -> + funnel0:funnel at 0,f6501000 { +> + funnel0:funnel@0,f6501000 { -funnel0 at f6501000. +funnel0@f6501000. > + compatible = "arm,coresight-funnel","arm,primecell"; > + reg = <0 0xf6501000 0 0x1000>; @@ -214,7 +214,7 @@ funnel0 at f6501000. > + #size-cells = <0>; > + > + /* funnel output port */ -> + port at 0 { +> + port@0 { > + reg = <0>; > + funnel0_out_port: endpoint { > + remote-endpoint = <&funnel1_in_port>; @@ -222,7 +222,7 @@ funnel0 at f6501000. > + }; > + > + /* funnel input ports */ -> + port at 1 { +> + port@1 { > + reg = <0>; > + funnel0_in_port0: endpoint { > + slave-mode; @@ -230,7 +230,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 2 { +> + port@2 { > + reg = <1>; > + funnel0_in_port1: endpoint { > + slave-mode; @@ -238,7 +238,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 3 { +> + port@3 { > + reg = <2>; > + funnel0_in_port2: endpoint { > + slave-mode; @@ -246,7 +246,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 4 { +> + port@4 { > + reg = <3>; > + funnel0_in_port3: endpoint { > + slave-mode; @@ -254,7 +254,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 5 { +> + port@5 { > + reg = <4>; > + funnel0_in_port4: endpoint { > + slave-mode; @@ -262,7 +262,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 6 { +> + port@6 { > + reg = <5>; > + funnel0_in_port5: endpoint { > + slave-mode; @@ -270,7 +270,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 7 { +> + port@7 { > + reg = <6>; > + funnel0_in_port6: endpoint { > + slave-mode; @@ -278,7 +278,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 8 { +> + port@8 { > + reg = <7>; > + funnel0_in_port7: endpoint { > + slave-mode; @@ -288,9 +288,9 @@ funnel0 at f6501000. > + }; > + }; > + -> + funnel1:funnel at 1,f6401000 { +> + funnel1:funnel@1,f6401000 { -funnel1 at f6401000 +funnel1@f6401000 > + compatible = "arm,coresight-funnel","arm,primecell"; > + reg = <0 0xf6401000 0 0x1000>; @@ -301,7 +301,7 @@ funnel1 at f6401000 > + #address-cells = <1>; > + #size-cells = <0>; > + /* funnel1 output port */ -> + port at 0 { +> + port@0 { > + reg = <0>; > + funnel1_out_port: endpoint { > + remote-endpoint = <&etf_in_port>; @@ -309,7 +309,7 @@ funnel1 at f6401000 > + }; > + > + /* funnel1 input port */ -> + port at 1 { +> + port@1 { > + reg = <0>; > + funnel1_in_port: endpoint { > + slave-mode; @@ -321,7 +321,7 @@ funnel1 at f6401000 Extra blank line. -> + etf:etf at 0,f6402000 { +> + etf:etf@0,f6402000 { > + compatible = "arm,coresight-tmc","arm,primecell"; > + reg = <0 0xf6402000 0 0x1000>; > + @@ -331,7 +331,7 @@ Extra blank line. > + #address-cells = <1>; > + #size-cells = <0>; > + /* etf input port */ -> + port at 0 { +> + port@0 { > + reg = <0>; > + etf_in_port: endpoint { > + slave-mode; @@ -339,7 +339,7 @@ Extra blank line. > + }; > + }; > + /* etf output port */ -> + port at 1 { +> + port@1 { > + reg = <0>; > + etf_out_port: endpoint { > + remote-endpoint = <&replicator0_in_port>; @@ -348,7 +348,7 @@ Extra blank line. > + }; > + }; > + -> + replicator at 0{ +> + replicator@0{ > + compatible = "arm,coresight-replicator"; > + > + clocks = <&sys_ctrl HI6220_CS_ATB>; @@ -357,7 +357,7 @@ Extra blank line. > + #address-cells = <1>; > + #size-cells = <0>; > + /* replicator input port */ -> + port at 0 { +> + port@0 { > + reg = <0>; > + replicator0_in_port: endpoint{ > + slave-mode; @@ -368,7 +368,7 @@ Wrong indent. > + }; > + }; > + /* replicator out port */ -> + port at 1 { +> + port@1 { > + reg = <0>; > + replicator0_out_port: endpoint { > + remote-endpoint = <&etr0_in_port>; @@ -377,7 +377,7 @@ Wrong indent. > + }; > + }; > + -> + etr at 0,f6404000 { +> + etr@0,f6404000 { > + compatible = "arm,coresight-tmc","arm,primecell"; > + reg = <0 0xf6404000 0 0x1000>; > + @@ -388,7 +388,7 @@ Wrong indent. > + #address-cells = <1>; > + #size-cells = <0>; > + /* etr input port */ -> + port at 0 { +> + port@0 { > + etr0_in_port: endpoint{ > + slave-mode; > + remote-endpoint = <&replicator0_out_port>; @@ -422,4 +422,8 @@ patch. > / { > -- > 2.1.0 -> +> +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 0374c73..04b67ca 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,21 @@ "ref\01491552418-74386-1-git-send-email-lipengcheng8@huawei.com\0" - "From\0leo.yan@linaro.org (Leo Yan)\0" - "Subject\0[PATCH] arm64: dts: Add coresight DT nodes for hi6220-hikey\0" + "ref\01491552418-74386-1-git-send-email-lipengcheng8-hv44wF8Li93QT0dZR+AlfA@public.gmane.org\0" + "From\0Leo Yan <leo.yan-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "Subject\0Re: [PATCH] arm64: dts: Add coresight DT nodes for hi6220-hikey\0" "Date\0Fri, 7 Apr 2017 17:38:11 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Li Pengcheng <lipengcheng8-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>\0" + "Cc\0xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org" + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + mark.rutland-5wv7dgnIgG8@public.gmane.org + catalin.marinas-5wv7dgnIgG8@public.gmane.org + will.deacon-5wv7dgnIgG8@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + dan.zhao-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + lizhong11-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org + " Mathieu Poirier <mathieu.poirier-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" "\00:1\0" "b\0" "Hi Pengcheng,\n" @@ -12,8 +25,8 @@ "On Fri, Apr 07, 2017 at 04:06:58PM +0800, Li Pengcheng wrote:\n" "> Add coresight DT nodes for hikey board.\n" "> \n" - "> Signed-off-by: Li Pengcheng <lipengcheng8@huawei.com>\n" - "> Signed-off-by: Li Zhong <lizhong11@hisilicon.com>\n" + "> Signed-off-by: Li Pengcheng <lipengcheng8-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>\n" + "> Signed-off-by: Li Zhong <lizhong11-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>\n" "> ---\n" "> .../arm64/boot/dts/hisilicon/hi6220-coresight.dtsi | 318 +++++++++++++++++++++\n" "> arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 1 +\n" @@ -30,7 +43,7 @@ "> + * Hisilicon Ltd. Hi6220 SoC\n" "> + *\n" "> + * Copyright (C) 2015-2016 Hisilicon Ltd.\n" - "> + * Author: lipengcheng <lipengcheng8@huawei.com>\n" + "> + * Author: lipengcheng <lipengcheng8-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>\n" "> + *\n" "> + * This program is free software; you can redistribute it and/or modify\n" "> + * it under the terms of the GNU General Public License version 2 as\n" @@ -63,9 +76,9 @@ "defined by its parent node.\n" "\n" "> +\t\tranges;\n" - "> +\t\tetm at 0,f659c000 {\n" + "> +\t\tetm@0,f659c000 {\n" "\n" - "Change to etm at f659c000?\n" + "Change to etm@f659c000?\n" "\n" "> +\t\t\tcompatible = \"arm,coresight-etm4x\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf659c000 0 0x1000>;\n" @@ -80,7 +93,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tetm at 1,f659d000 {\n" + "> +\t\tetm@1,f659d000 {\n" "\n" "Same with above.\n" "\n" @@ -98,7 +111,7 @@ "> +\n" "> +\t\t};\n" "> +\n" - "> +\t\tetm at 2,f659e000 {\n" + "> +\t\tetm@2,f659e000 {\n" "\n" "Same with above.\n" "\n" @@ -115,7 +128,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tetm at 3,f659f000 {\n" + "> +\t\tetm@3,f659f000 {\n" "\n" "Same with above.\n" "\n" @@ -133,7 +146,7 @@ "> +\t\t};\n" "> +\n" "> +\t\t/* A53 cluster1 internal coresight */\n" - "> +\t\tetm at 4,f65dc000 {\n" + "> +\t\tetm@4,f65dc000 {\n" "\n" "Same with above.\n" "\n" @@ -153,7 +166,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tetm at 5,f65dd000 {\n" + "> +\t\tetm@5,f65dd000 {\n" "\n" "Same with above.\n" "\n" @@ -173,9 +186,9 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tetm at 6,f65de000 {\n" + "> +\t\tetm@6,f65de000 {\n" "\n" - "Change to etm at f65de000?\n" + "Change to etm@f65de000?\n" "\n" "> +\t\t\tcompatible = \"arm,coresight-etm4x\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf65de000 0 0x1000>;\n" @@ -190,7 +203,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tetm at 7,f65df000 {\n" + "> +\t\tetm@7,f65df000 {\n" "\n" "Same with above.\n" "\n" @@ -207,9 +220,9 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tfunnel0:funnel at 0,f6501000 {\n" + "> +\t\tfunnel0:funnel@0,f6501000 {\n" "\n" - "funnel0 at f6501000.\n" + "funnel0@f6501000.\n" "\n" "> +\t\t\tcompatible = \"arm,coresight-funnel\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6501000 0 0x1000>;\n" @@ -221,7 +234,7 @@ "> +\t\t\t\t#size-cells = <0>;\n" "> +\n" "> +\t\t\t\t/* funnel output port */\n" - "> +\t\t\t\tport at 0 {\n" + "> +\t\t\t\tport@0 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\tfunnel0_out_port: endpoint {\n" "> +\t\t\t\t\t\tremote-endpoint = <&funnel1_in_port>;\n" @@ -229,7 +242,7 @@ "> +\t\t\t\t};\n" "> +\n" "> +\t\t\t\t/* funnel input ports */\n" - "> +\t\t\t\tport at 1 {\n" + "> +\t\t\t\tport@1 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\tfunnel0_in_port0: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -237,7 +250,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 2 {\n" + "> +\t\t\t\tport@2 {\n" "> +\t\t\t\t\treg = <1>;\n" "> +\t\t\t\t\tfunnel0_in_port1: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -245,7 +258,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 3 {\n" + "> +\t\t\t\tport@3 {\n" "> +\t\t\t\t\treg = <2>;\n" "> +\t\t\t\t\tfunnel0_in_port2: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -253,7 +266,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 4 {\n" + "> +\t\t\t\tport@4 {\n" "> +\t\t\t\t\treg = <3>;\n" "> +\t\t\t\t\tfunnel0_in_port3: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -261,7 +274,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 5 {\n" + "> +\t\t\t\tport@5 {\n" "> +\t\t\t\t\treg = <4>;\n" "> +\t\t\t\t\tfunnel0_in_port4: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -269,7 +282,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 6 {\n" + "> +\t\t\t\tport@6 {\n" "> +\t\t\t\t\treg = <5>;\n" "> +\t\t\t\t\tfunnel0_in_port5: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -277,7 +290,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 7 {\n" + "> +\t\t\t\tport@7 {\n" "> +\t\t\t\t\treg = <6>;\n" "> +\t\t\t\t\tfunnel0_in_port6: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -285,7 +298,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 8 {\n" + "> +\t\t\t\tport@8 {\n" "> +\t\t\t\t\treg = <7>;\n" "> +\t\t\t\t\tfunnel0_in_port7: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -295,9 +308,9 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tfunnel1:funnel at 1,f6401000 {\n" + "> +\t\tfunnel1:funnel@1,f6401000 {\n" "\n" - "funnel1 at f6401000\n" + "funnel1@f6401000\n" "\n" "> +\t\t\tcompatible = \"arm,coresight-funnel\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6401000 0 0x1000>;\n" @@ -308,7 +321,7 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\t\t\t\t/* funnel1 output port */\n" - "> +\t\t\t\tport at 0 {\n" + "> +\t\t\t\tport@0 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\tfunnel1_out_port: endpoint {\n" "> +\t\t\t\t\t\tremote-endpoint = <&etf_in_port>;\n" @@ -316,7 +329,7 @@ "> +\t\t\t\t};\n" "> +\n" "> +\t\t\t\t/* funnel1 input port */\n" - "> +\t\t\t\tport at 1 {\n" + "> +\t\t\t\tport@1 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\tfunnel1_in_port: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -328,7 +341,7 @@ "\n" "Extra blank line.\n" "\n" - "> +\t\tetf:etf at 0,f6402000 {\n" + "> +\t\tetf:etf@0,f6402000 {\n" "> +\t\t\tcompatible = \"arm,coresight-tmc\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6402000 0 0x1000>;\n" "> +\n" @@ -338,7 +351,7 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\t\t\t\t/* etf input port */\n" - "> +\t\t\t\tport at 0 {\n" + "> +\t\t\t\tport@0 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\tetf_in_port: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -346,7 +359,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\t\t\t\t/* etf output port */\n" - "> +\t\t\t\tport at 1 {\n" + "> +\t\t\t\tport@1 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\tetf_out_port: endpoint {\n" "> +\t\t\t\t\t\tremote-endpoint = <&replicator0_in_port>;\n" @@ -355,7 +368,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\treplicator at 0{\n" + "> +\t\treplicator@0{\n" "> +\t\t\tcompatible = \"arm,coresight-replicator\";\n" "> +\n" "> +\t\t\tclocks = <&sys_ctrl HI6220_CS_ATB>;\n" @@ -364,7 +377,7 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\t\t\t\t/* replicator input port */\n" - "> +\t\t\t\tport at 0 {\n" + "> +\t\t\t\tport@0 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\treplicator0_in_port: endpoint{\n" "> +\t\t\t\t\tslave-mode;\n" @@ -375,7 +388,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\t\t\t\t/* replicator out port */\n" - "> +\t\t\t\tport at 1 {\n" + "> +\t\t\t\tport@1 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\treplicator0_out_port: endpoint {\n" "> +\t\t\t\t\t\tremote-endpoint = <&etr0_in_port>;\n" @@ -384,7 +397,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tetr at 0,f6404000 {\n" + "> +\t\tetr@0,f6404000 {\n" "> +\t\t\tcompatible = \"arm,coresight-tmc\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6404000 0 0x1000>;\n" "> +\n" @@ -395,7 +408,7 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\t\t\t\t/* etr input port */\n" - "> +\t\t\t\tport at 0 {\n" + "> +\t\t\t\tport@0 {\n" "> +\t\t\t\t\tetr0_in_port: endpoint{\n" "> +\t\t\t\t\tslave-mode;\n" "> +\t\t\t\t\tremote-endpoint = <&replicator0_out_port>;\n" @@ -429,6 +442,10 @@ "> / {\n" "> -- \n" "> 2.1.0\n" - > + "> \n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -5b57df2124f3b869d0ad20465d9d19aa38e7255772968e79754c3b4f76b4d12b +7eebf1ec0cf8a013267372d6b228fc8d00d55ce90a3c65234de58020ecd7747f
diff --git a/a/1.txt b/N2/1.txt index 1332fad..2699c86 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -56,9 +56,9 @@ I think "#address-cells" and "#size-cells" also can remove. This is defined by its parent node. > + ranges; -> + etm at 0,f659c000 { +> + etm@0,f659c000 { -Change to etm at f659c000? +Change to etm@f659c000? > + compatible = "arm,coresight-etm4x","arm,primecell"; > + reg = <0 0xf659c000 0 0x1000>; @@ -73,7 +73,7 @@ Change to etm at f659c000? > + }; > + }; > + -> + etm at 1,f659d000 { +> + etm@1,f659d000 { Same with above. @@ -91,7 +91,7 @@ Same with above. > + > + }; > + -> + etm at 2,f659e000 { +> + etm@2,f659e000 { Same with above. @@ -108,7 +108,7 @@ Same with above. > + }; > + }; > + -> + etm at 3,f659f000 { +> + etm@3,f659f000 { Same with above. @@ -126,7 +126,7 @@ Same with above. > + }; > + > + /* A53 cluster1 internal coresight */ -> + etm at 4,f65dc000 { +> + etm@4,f65dc000 { Same with above. @@ -146,7 +146,7 @@ Wrong indent. > + }; > + }; > + -> + etm at 5,f65dd000 { +> + etm@5,f65dd000 { Same with above. @@ -166,9 +166,9 @@ Wrong indent. > + }; > + }; > + -> + etm at 6,f65de000 { +> + etm@6,f65de000 { -Change to etm at f65de000? +Change to etm@f65de000? > + compatible = "arm,coresight-etm4x","arm,primecell"; > + reg = <0 0xf65de000 0 0x1000>; @@ -183,7 +183,7 @@ Change to etm at f65de000? > + }; > + }; > + -> + etm at 7,f65df000 { +> + etm@7,f65df000 { Same with above. @@ -200,9 +200,9 @@ Same with above. > + }; > + }; > + -> + funnel0:funnel at 0,f6501000 { +> + funnel0:funnel@0,f6501000 { -funnel0 at f6501000. +funnel0@f6501000. > + compatible = "arm,coresight-funnel","arm,primecell"; > + reg = <0 0xf6501000 0 0x1000>; @@ -214,7 +214,7 @@ funnel0 at f6501000. > + #size-cells = <0>; > + > + /* funnel output port */ -> + port at 0 { +> + port@0 { > + reg = <0>; > + funnel0_out_port: endpoint { > + remote-endpoint = <&funnel1_in_port>; @@ -222,7 +222,7 @@ funnel0 at f6501000. > + }; > + > + /* funnel input ports */ -> + port at 1 { +> + port@1 { > + reg = <0>; > + funnel0_in_port0: endpoint { > + slave-mode; @@ -230,7 +230,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 2 { +> + port@2 { > + reg = <1>; > + funnel0_in_port1: endpoint { > + slave-mode; @@ -238,7 +238,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 3 { +> + port@3 { > + reg = <2>; > + funnel0_in_port2: endpoint { > + slave-mode; @@ -246,7 +246,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 4 { +> + port@4 { > + reg = <3>; > + funnel0_in_port3: endpoint { > + slave-mode; @@ -254,7 +254,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 5 { +> + port@5 { > + reg = <4>; > + funnel0_in_port4: endpoint { > + slave-mode; @@ -262,7 +262,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 6 { +> + port@6 { > + reg = <5>; > + funnel0_in_port5: endpoint { > + slave-mode; @@ -270,7 +270,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 7 { +> + port@7 { > + reg = <6>; > + funnel0_in_port6: endpoint { > + slave-mode; @@ -278,7 +278,7 @@ funnel0 at f6501000. > + }; > + }; > + -> + port at 8 { +> + port@8 { > + reg = <7>; > + funnel0_in_port7: endpoint { > + slave-mode; @@ -288,9 +288,9 @@ funnel0 at f6501000. > + }; > + }; > + -> + funnel1:funnel at 1,f6401000 { +> + funnel1:funnel@1,f6401000 { -funnel1 at f6401000 +funnel1@f6401000 > + compatible = "arm,coresight-funnel","arm,primecell"; > + reg = <0 0xf6401000 0 0x1000>; @@ -301,7 +301,7 @@ funnel1 at f6401000 > + #address-cells = <1>; > + #size-cells = <0>; > + /* funnel1 output port */ -> + port at 0 { +> + port@0 { > + reg = <0>; > + funnel1_out_port: endpoint { > + remote-endpoint = <&etf_in_port>; @@ -309,7 +309,7 @@ funnel1 at f6401000 > + }; > + > + /* funnel1 input port */ -> + port at 1 { +> + port@1 { > + reg = <0>; > + funnel1_in_port: endpoint { > + slave-mode; @@ -321,7 +321,7 @@ funnel1 at f6401000 Extra blank line. -> + etf:etf at 0,f6402000 { +> + etf:etf@0,f6402000 { > + compatible = "arm,coresight-tmc","arm,primecell"; > + reg = <0 0xf6402000 0 0x1000>; > + @@ -331,7 +331,7 @@ Extra blank line. > + #address-cells = <1>; > + #size-cells = <0>; > + /* etf input port */ -> + port at 0 { +> + port@0 { > + reg = <0>; > + etf_in_port: endpoint { > + slave-mode; @@ -339,7 +339,7 @@ Extra blank line. > + }; > + }; > + /* etf output port */ -> + port at 1 { +> + port@1 { > + reg = <0>; > + etf_out_port: endpoint { > + remote-endpoint = <&replicator0_in_port>; @@ -348,7 +348,7 @@ Extra blank line. > + }; > + }; > + -> + replicator at 0{ +> + replicator@0{ > + compatible = "arm,coresight-replicator"; > + > + clocks = <&sys_ctrl HI6220_CS_ATB>; @@ -357,7 +357,7 @@ Extra blank line. > + #address-cells = <1>; > + #size-cells = <0>; > + /* replicator input port */ -> + port at 0 { +> + port@0 { > + reg = <0>; > + replicator0_in_port: endpoint{ > + slave-mode; @@ -368,7 +368,7 @@ Wrong indent. > + }; > + }; > + /* replicator out port */ -> + port at 1 { +> + port@1 { > + reg = <0>; > + replicator0_out_port: endpoint { > + remote-endpoint = <&etr0_in_port>; @@ -377,7 +377,7 @@ Wrong indent. > + }; > + }; > + -> + etr at 0,f6404000 { +> + etr@0,f6404000 { > + compatible = "arm,coresight-tmc","arm,primecell"; > + reg = <0 0xf6404000 0 0x1000>; > + @@ -388,7 +388,7 @@ Wrong indent. > + #address-cells = <1>; > + #size-cells = <0>; > + /* etr input port */ -> + port at 0 { +> + port@0 { > + etr0_in_port: endpoint{ > + slave-mode; > + remote-endpoint = <&replicator0_out_port>; diff --git a/a/content_digest b/N2/content_digest index 0374c73..006923b 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,8 +1,20 @@ "ref\01491552418-74386-1-git-send-email-lipengcheng8@huawei.com\0" - "From\0leo.yan@linaro.org (Leo Yan)\0" - "Subject\0[PATCH] arm64: dts: Add coresight DT nodes for hi6220-hikey\0" + "From\0Leo Yan <leo.yan@linaro.org>\0" + "Subject\0Re: [PATCH] arm64: dts: Add coresight DT nodes for hi6220-hikey\0" "Date\0Fri, 7 Apr 2017 17:38:11 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Li Pengcheng <lipengcheng8@huawei.com>\0" + "Cc\0xuwei5@hisilicon.com" + robh+dt@kernel.org + mark.rutland@arm.com + catalin.marinas@arm.com + will.deacon@arm.com + linux-arm-kernel@lists.infradead.org + devicetree@vger.kernel.org + linux-kernel@vger.kernel.org + suzhuangluan@hisilicon.com + dan.zhao@hisilicon.com + lizhong11@hisilicon.com + " Mathieu Poirier <mathieu.poirier@linaro.org>\0" "\00:1\0" "b\0" "Hi Pengcheng,\n" @@ -63,9 +75,9 @@ "defined by its parent node.\n" "\n" "> +\t\tranges;\n" - "> +\t\tetm at 0,f659c000 {\n" + "> +\t\tetm@0,f659c000 {\n" "\n" - "Change to etm at f659c000?\n" + "Change to etm@f659c000?\n" "\n" "> +\t\t\tcompatible = \"arm,coresight-etm4x\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf659c000 0 0x1000>;\n" @@ -80,7 +92,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tetm at 1,f659d000 {\n" + "> +\t\tetm@1,f659d000 {\n" "\n" "Same with above.\n" "\n" @@ -98,7 +110,7 @@ "> +\n" "> +\t\t};\n" "> +\n" - "> +\t\tetm at 2,f659e000 {\n" + "> +\t\tetm@2,f659e000 {\n" "\n" "Same with above.\n" "\n" @@ -115,7 +127,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tetm at 3,f659f000 {\n" + "> +\t\tetm@3,f659f000 {\n" "\n" "Same with above.\n" "\n" @@ -133,7 +145,7 @@ "> +\t\t};\n" "> +\n" "> +\t\t/* A53 cluster1 internal coresight */\n" - "> +\t\tetm at 4,f65dc000 {\n" + "> +\t\tetm@4,f65dc000 {\n" "\n" "Same with above.\n" "\n" @@ -153,7 +165,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tetm at 5,f65dd000 {\n" + "> +\t\tetm@5,f65dd000 {\n" "\n" "Same with above.\n" "\n" @@ -173,9 +185,9 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tetm at 6,f65de000 {\n" + "> +\t\tetm@6,f65de000 {\n" "\n" - "Change to etm at f65de000?\n" + "Change to etm@f65de000?\n" "\n" "> +\t\t\tcompatible = \"arm,coresight-etm4x\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf65de000 0 0x1000>;\n" @@ -190,7 +202,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tetm at 7,f65df000 {\n" + "> +\t\tetm@7,f65df000 {\n" "\n" "Same with above.\n" "\n" @@ -207,9 +219,9 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tfunnel0:funnel at 0,f6501000 {\n" + "> +\t\tfunnel0:funnel@0,f6501000 {\n" "\n" - "funnel0 at f6501000.\n" + "funnel0@f6501000.\n" "\n" "> +\t\t\tcompatible = \"arm,coresight-funnel\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6501000 0 0x1000>;\n" @@ -221,7 +233,7 @@ "> +\t\t\t\t#size-cells = <0>;\n" "> +\n" "> +\t\t\t\t/* funnel output port */\n" - "> +\t\t\t\tport at 0 {\n" + "> +\t\t\t\tport@0 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\tfunnel0_out_port: endpoint {\n" "> +\t\t\t\t\t\tremote-endpoint = <&funnel1_in_port>;\n" @@ -229,7 +241,7 @@ "> +\t\t\t\t};\n" "> +\n" "> +\t\t\t\t/* funnel input ports */\n" - "> +\t\t\t\tport at 1 {\n" + "> +\t\t\t\tport@1 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\tfunnel0_in_port0: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -237,7 +249,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 2 {\n" + "> +\t\t\t\tport@2 {\n" "> +\t\t\t\t\treg = <1>;\n" "> +\t\t\t\t\tfunnel0_in_port1: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -245,7 +257,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 3 {\n" + "> +\t\t\t\tport@3 {\n" "> +\t\t\t\t\treg = <2>;\n" "> +\t\t\t\t\tfunnel0_in_port2: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -253,7 +265,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 4 {\n" + "> +\t\t\t\tport@4 {\n" "> +\t\t\t\t\treg = <3>;\n" "> +\t\t\t\t\tfunnel0_in_port3: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -261,7 +273,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 5 {\n" + "> +\t\t\t\tport@5 {\n" "> +\t\t\t\t\treg = <4>;\n" "> +\t\t\t\t\tfunnel0_in_port4: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -269,7 +281,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 6 {\n" + "> +\t\t\t\tport@6 {\n" "> +\t\t\t\t\treg = <5>;\n" "> +\t\t\t\t\tfunnel0_in_port5: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -277,7 +289,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 7 {\n" + "> +\t\t\t\tport@7 {\n" "> +\t\t\t\t\treg = <6>;\n" "> +\t\t\t\t\tfunnel0_in_port6: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -285,7 +297,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tport at 8 {\n" + "> +\t\t\t\tport@8 {\n" "> +\t\t\t\t\treg = <7>;\n" "> +\t\t\t\t\tfunnel0_in_port7: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -295,9 +307,9 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tfunnel1:funnel at 1,f6401000 {\n" + "> +\t\tfunnel1:funnel@1,f6401000 {\n" "\n" - "funnel1 at f6401000\n" + "funnel1@f6401000\n" "\n" "> +\t\t\tcompatible = \"arm,coresight-funnel\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6401000 0 0x1000>;\n" @@ -308,7 +320,7 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\t\t\t\t/* funnel1 output port */\n" - "> +\t\t\t\tport at 0 {\n" + "> +\t\t\t\tport@0 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\tfunnel1_out_port: endpoint {\n" "> +\t\t\t\t\t\tremote-endpoint = <&etf_in_port>;\n" @@ -316,7 +328,7 @@ "> +\t\t\t\t};\n" "> +\n" "> +\t\t\t\t/* funnel1 input port */\n" - "> +\t\t\t\tport at 1 {\n" + "> +\t\t\t\tport@1 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\tfunnel1_in_port: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -328,7 +340,7 @@ "\n" "Extra blank line.\n" "\n" - "> +\t\tetf:etf at 0,f6402000 {\n" + "> +\t\tetf:etf@0,f6402000 {\n" "> +\t\t\tcompatible = \"arm,coresight-tmc\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6402000 0 0x1000>;\n" "> +\n" @@ -338,7 +350,7 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\t\t\t\t/* etf input port */\n" - "> +\t\t\t\tport at 0 {\n" + "> +\t\t\t\tport@0 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\tetf_in_port: endpoint {\n" "> +\t\t\t\t\t\tslave-mode;\n" @@ -346,7 +358,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\t\t\t\t/* etf output port */\n" - "> +\t\t\t\tport at 1 {\n" + "> +\t\t\t\tport@1 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\tetf_out_port: endpoint {\n" "> +\t\t\t\t\t\tremote-endpoint = <&replicator0_in_port>;\n" @@ -355,7 +367,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\treplicator at 0{\n" + "> +\t\treplicator@0{\n" "> +\t\t\tcompatible = \"arm,coresight-replicator\";\n" "> +\n" "> +\t\t\tclocks = <&sys_ctrl HI6220_CS_ATB>;\n" @@ -364,7 +376,7 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\t\t\t\t/* replicator input port */\n" - "> +\t\t\t\tport at 0 {\n" + "> +\t\t\t\tport@0 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\treplicator0_in_port: endpoint{\n" "> +\t\t\t\t\tslave-mode;\n" @@ -375,7 +387,7 @@ "> +\t\t\t\t\t};\n" "> +\t\t\t\t};\n" "> +\t\t\t\t/* replicator out port */\n" - "> +\t\t\t\tport at 1 {\n" + "> +\t\t\t\tport@1 {\n" "> +\t\t\t\t\treg = <0>;\n" "> +\t\t\t\t\treplicator0_out_port: endpoint {\n" "> +\t\t\t\t\t\tremote-endpoint = <&etr0_in_port>;\n" @@ -384,7 +396,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tetr at 0,f6404000 {\n" + "> +\t\tetr@0,f6404000 {\n" "> +\t\t\tcompatible = \"arm,coresight-tmc\",\"arm,primecell\";\n" "> +\t\t\treg = <0 0xf6404000 0 0x1000>;\n" "> +\n" @@ -395,7 +407,7 @@ "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" "> +\t\t\t\t/* etr input port */\n" - "> +\t\t\t\tport at 0 {\n" + "> +\t\t\t\tport@0 {\n" "> +\t\t\t\t\tetr0_in_port: endpoint{\n" "> +\t\t\t\t\tslave-mode;\n" "> +\t\t\t\t\tremote-endpoint = <&replicator0_out_port>;\n" @@ -431,4 +443,4 @@ "> 2.1.0\n" > -5b57df2124f3b869d0ad20465d9d19aa38e7255772968e79754c3b4f76b4d12b +7ffbbdff92fd8e21f97c45a99e43b887dfeedebf536a7006a7a1b1795a133827
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