From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Subject: Re: [PATCH] drm: panels: Add MAINTAINERS entry for LVS panel driver Date: Tue, 11 Apr 2017 12:03:43 +0200 Message-ID: <20170411100342.GE6484@ulmo.ba.sec> References: <10367276.mxSL6V0lE5@avalon> <20170410071758.GA7819@ulmo.ba.sec> <1491818318.2270.26.camel@pengutronix.de> <3355213.1Mfthv3hYv@avalon> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1374729217==" Return-path: Received: from hqemgate14.nvidia.com (hqemgate14.nvidia.com [216.228.121.143]) by gabe.freedesktop.org (Postfix) with ESMTPS id B54656E43C for ; Tue, 11 Apr 2017 10:05:53 +0000 (UTC) In-Reply-To: <3355213.1Mfthv3hYv@avalon> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Laurent Pinchart Cc: Laurent Pinchart , Emil Velikov , dri-devel List-Id: dri-devel@lists.freedesktop.org --===============1374729217== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="jKBxcB1XkHIR0Eqt" Content-Disposition: inline --jKBxcB1XkHIR0Eqt Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Apr 11, 2017 at 08:00:11AM +0300, Laurent Pinchart wrote: [...] > The point I don't agree with is that timings have to be specified in C co= de.=20 > As pointed in in a comment to > https://sietch-tagr.blogspot.fi/2016/04/display-panels-are-not-special.ht= ml, > there's a huge number of display panels on the=20 > marked, and the Linux kernel supports only a very tiny fraction of them. = I=20 > still haven't seen the scalability issue of a C mode DB being addressed, = and=20 > that's a major blocker for me. How about we tackle that problem when it becomes real? drm/panel has existed for about 3.5 years now and we support not even 100 different panels. > The other comment about EMC and EMI (Electro- > Magnetic Compatibility and Electro-Magnetic Interference) is also valid i= n my=20 > opinion, and is why we had to specify clock frequencies in DT for cameras= as=20 > they need to be fine-tuned for each particular system. The same applies t= o=20 > panels, where timings for the same panel integrated in different systems = may=20 > need to differ. We already have a mechanism to do this. Initially panel descriptors used to contain a single mode, but it wasn't very long until we encountered a situation where the same panel was used on different devices with slight differences in capabilities, which cause the original mode not to work. The solution that Philipp Zabel came up with is fairly elegant. Instead of specifying a single mode, matching essentially the integration on one board, panel descriptors can now contain display timing ranges. This allows each display controller driver to tailor a mode that fits its needs. Thierry --jKBxcB1XkHIR0Eqt Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAljsqfwACgkQ3SOs138+ s6FwIBAAknTBWVixBanxuuifgiyfy6dFvCBQzuI6hFNoTkqxkpURUuey21RP5RC8 mvs/qTRRvVCWtQdIgtBLktDO+cJcaR1E8vZssLM4wlsUrXKK+1oEgw6mZ8oLkXjO +Dq5+9EfaBH16yDnqc5Xqstqh/B+l4T+wMCSg7RyWmJjWBehYk84EJGFT4fuhASC WnMOEkLOblu1Zz1acV+tszEAxx0yPl13Pz87WDXPnrXDmoMrrIEnwQLRmDBg48Xd z32ceMosM6w8wmg299eejzF+X+aKqIkMFClTdv21ialaKUy2uC3ad78w3C8H8WKV geIHqfE6vZh1BTETlbYLA/GgkD7PEJbqsYlVhg3HKAoElqh94Afn8PzHiobVVMFb 65QncdqRUgwCNgsW6qtg1GIE/05uxKwXYii16ti9kSZguwD4mpQyZjo7J5Y9+I5m eNLEbD+y7RNsfuAjjnhd/7gVBjbXGr1RU9egsRGHdaZSVJnqdvb+oOY91OrdZmAG wqsJ0WrDK27nNbdplTFV5tG1TXXmKl6Ll2uJ0kaGeRWiCQF8Xai3jYjW3rOPjNCM HPUmWByLB67ieItnmocmate2Sd88in4VQ46fEsdKeRQQ4rTIXhkMuGKJnA/k6WJa DqDbTEXurLK7E89EHMXEBrAQH6onIhFKmbnwNtHs0lPT/BoYa7o= =hnl0 -----END PGP SIGNATURE----- --jKBxcB1XkHIR0Eqt-- --===============1374729217== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== --===============1374729217==--