diff for duplicates of <20170428185349.GD7065@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index 540e4d3..d652f01 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -243,7 +243,3 @@ Not 32765 or 32768? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project --- -To unsubscribe from this list: send the line "unsubscribe devicetree" in -the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org -More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 218ebf4..b1d3071 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,29 +1,28 @@ "ref\01493373403-23462-1-git-send-email-varada@codeaurora.org\0" "ref\01493373403-23462-5-git-send-email-varada@codeaurora.org\0" - "ref\01493373403-23462-5-git-send-email-varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org\0" - "From\0Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" + "From\0Stephen Boyd <sboyd@codeaurora.org>\0" "Subject\0Re: [PATCH 4/5] arm64: dts: Add ipq8074 SoC and MTP board support\0" "Date\0Fri, 28 Apr 2017 11:53:49 -0700\0" - "To\0Varadarajan Narayanan <varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" - "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" - mark.rutland-5wv7dgnIgG8@public.gmane.org - mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org - linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - andy.gross-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - david.brown-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - catalin.marinas-5wv7dgnIgG8@public.gmane.org - will.deacon-5wv7dgnIgG8@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - sjaganat-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - " Manoharan Vijaya Raghavan <mraghava-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" + "To\0Varadarajan Narayanan <varada@codeaurora.org>\0" + "Cc\0robh+dt@kernel.org" + mark.rutland@arm.com + mturquette@baylibre.com + linus.walleij@linaro.org + andy.gross@linaro.org + david.brown@linaro.org + catalin.marinas@arm.com + will.deacon@arm.com + devicetree@vger.kernel.org + linux-kernel@vger.kernel.org + linux-clk@vger.kernel.org + linux-gpio@vger.kernel.org + linux-arm-msm@vger.kernel.org + linux-soc@vger.kernel.org + linux-arm-kernel@lists.infradead.org + sricharan@codeaurora.org + absahu@codeaurora.org + sjaganat@codeaurora.org + " Manoharan Vijaya Raghavan <mraghava@codeaurora.org>\0" "\00:1\0" "b\0" "On 04/28, Varadarajan Narayanan wrote:\n" @@ -270,10 +269,6 @@ "\n" "-- \n" "Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,\n" - "a Linux Foundation Collaborative Project\n" - "--\n" - "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" - "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" - More majordomo info at http://vger.kernel.org/majordomo-info.html + a Linux Foundation Collaborative Project -3a6355faa0eacfc56e0f43d7752d6610127c4a344765589fb9d611b6ef91c754 +00e1b868a91e78b9d9b95124ab2c15fcb19d111b69857e323f3e89ae740f1b8a
diff --git a/a/1.txt b/N2/1.txt index 540e4d3..869e40e 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -42,7 +42,7 @@ Add an aliases node for serial0 and use a chosen node with stdout-path = "serial Do you need the soc label here? Please remove. -> + pinctrl@1000000 { +> + pinctrl at 1000000 { > + serial_4_pins: serial4_pinmux { > + mux { > + pins = "gpio23", "gpio24"; @@ -52,7 +52,7 @@ Do you need the soc label here? Please remove. > + }; > + }; > + -> + serial@78b3000 { +> + serial at 78b3000 { > + pinctrl-0 = <&serial_4_pins>; > + pinctrl-names = "default"; > + status = "ok"; @@ -91,7 +91,7 @@ Do you need the soc label here? Please remove. > + ranges = <0 0 0 0xffffffff>; > + compatible = "simple-bus"; > + -> + pinctrl@1000000 { +> + pinctrl at 1000000 { > + compatible = "qcom,ipq8074-pinctrl"; > + reg = <0x1000000 0x300000>; > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; @@ -101,7 +101,7 @@ Do you need the soc label here? Please remove. > + #interrupt-cells = <0x2>; > + }; > + -> + intc: interrupt-controller@b000000 { +> + intc: interrupt-controller at b000000 { > + compatible = "qcom,msm-qgic2"; > + interrupt-controller; > + #interrupt-cells = <0x3>; @@ -123,7 +123,7 @@ Please align this up with previous reg property. Is there an mmio timer as well? We should add it too. > + -> + gcc: gcc@1800000 { +> + gcc: gcc at 1800000 { > + compatible = "qcom,gcc-ipq8074"; > + reg = <0x1800000 0x80000>; @@ -133,7 +133,7 @@ Wow that is a huge area! Is it really that large? > + #reset-cells = <0x1>; > + }; > + -> + serial@78b3000 { +> + serial at 78b3000 { > + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; > + reg = <0x78b3000 0x200>; > + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; @@ -174,7 +174,7 @@ Is this needed? Looks ok, but just curious if we need to do it for other arm64 platforms we support. > + -> + CPU0: cpu@0 { +> + CPU0: cpu at 0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0>; @@ -182,7 +182,7 @@ for other arm64 platforms we support. > + enable-method = "psci"; > + }; > + -> + CPU1: cpu@1 { +> + CPU1: cpu at 1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + enable-method = "psci"; @@ -190,7 +190,7 @@ for other arm64 platforms we support. > + next-level-cache = <&L2_0>; > + }; > + -> + CPU2: cpu@2 { +> + CPU2: cpu at 2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + enable-method = "psci"; @@ -198,7 +198,7 @@ for other arm64 platforms we support. > + next-level-cache = <&L2_0>; > + }; > + -> + CPU3: cpu@3 { +> + CPU3: cpu at 3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + enable-method = "psci"; @@ -243,7 +243,3 @@ Not 32765 or 32768? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project --- -To unsubscribe from this list: send the line "unsubscribe devicetree" in -the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org -More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N2/content_digest index 218ebf4..9dda7a6 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,29 +1,9 @@ "ref\01493373403-23462-1-git-send-email-varada@codeaurora.org\0" "ref\01493373403-23462-5-git-send-email-varada@codeaurora.org\0" - "ref\01493373403-23462-5-git-send-email-varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org\0" - "From\0Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" - "Subject\0Re: [PATCH 4/5] arm64: dts: Add ipq8074 SoC and MTP board support\0" + "From\0sboyd@codeaurora.org (Stephen Boyd)\0" + "Subject\0[PATCH 4/5] arm64: dts: Add ipq8074 SoC and MTP board support\0" "Date\0Fri, 28 Apr 2017 11:53:49 -0700\0" - "To\0Varadarajan Narayanan <varada-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" - "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" - mark.rutland-5wv7dgnIgG8@public.gmane.org - mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org - linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - andy.gross-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - david.brown-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - catalin.marinas-5wv7dgnIgG8@public.gmane.org - will.deacon-5wv7dgnIgG8@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - sricharan-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - absahu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - sjaganat-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - " Manoharan Vijaya Raghavan <mraghava-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 04/28, Varadarajan Narayanan wrote:\n" @@ -70,7 +50,7 @@ "\n" "Do you need the soc label here? Please remove.\n" "\n" - "> +\t\tpinctrl@1000000 {\n" + "> +\t\tpinctrl at 1000000 {\n" "> +\t\t\tserial_4_pins: serial4_pinmux {\n" "> +\t\t\t\tmux {\n" "> +\t\t\t\t\tpins = \"gpio23\", \"gpio24\";\n" @@ -80,7 +60,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tserial@78b3000 {\n" + "> +\t\tserial at 78b3000 {\n" "> +\t\t\tpinctrl-0 = <&serial_4_pins>;\n" "> +\t\t\tpinctrl-names = \"default\";\n" "> +\t\t\tstatus = \"ok\";\n" @@ -119,7 +99,7 @@ "> +\t\tranges = <0 0 0 0xffffffff>;\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\n" - "> +\t\tpinctrl@1000000 {\n" + "> +\t\tpinctrl at 1000000 {\n" "> +\t\t\tcompatible = \"qcom,ipq8074-pinctrl\";\n" "> +\t\t\treg = <0x1000000 0x300000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -129,7 +109,7 @@ "> +\t\t\t#interrupt-cells = <0x2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tintc: interrupt-controller@b000000 {\n" + "> +\t\tintc: interrupt-controller at b000000 {\n" "> +\t\t\tcompatible = \"qcom,msm-qgic2\";\n" "> +\t\t\tinterrupt-controller;\n" "> +\t\t\t#interrupt-cells = <0x3>;\n" @@ -151,7 +131,7 @@ "Is there an mmio timer as well? We should add it too.\n" "\n" "> +\n" - "> +\t\tgcc: gcc@1800000 {\n" + "> +\t\tgcc: gcc at 1800000 {\n" "> +\t\t\tcompatible = \"qcom,gcc-ipq8074\";\n" "> +\t\t\treg = <0x1800000 0x80000>;\n" "\n" @@ -161,7 +141,7 @@ "> +\t\t\t#reset-cells = <0x1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tserial@78b3000 {\n" + "> +\t\tserial at 78b3000 {\n" "> +\t\t\tcompatible = \"qcom,msm-uartdm-v1.4\", \"qcom,msm-uartdm\";\n" "> +\t\t\treg = <0x78b3000 0x200>;\n" "> +\t\t\tinterrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -202,7 +182,7 @@ "for other arm64 platforms we support.\n" "\n" "> +\n" - "> +\t\tCPU0: cpu@0 {\n" + "> +\t\tCPU0: cpu at 0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\treg = <0x0>;\n" @@ -210,7 +190,7 @@ "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tCPU1: cpu@1 {\n" + "> +\t\tCPU1: cpu at 1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -218,7 +198,7 @@ "> +\t\t\tnext-level-cache = <&L2_0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tCPU2: cpu@2 {\n" + "> +\t\tCPU2: cpu at 2 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -226,7 +206,7 @@ "> +\t\t\tnext-level-cache = <&L2_0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tCPU3: cpu@3 {\n" + "> +\t\tCPU3: cpu at 3 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tenable-method = \"psci\";\n" @@ -270,10 +250,6 @@ "\n" "-- \n" "Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,\n" - "a Linux Foundation Collaborative Project\n" - "--\n" - "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" - "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" - More majordomo info at http://vger.kernel.org/majordomo-info.html + a Linux Foundation Collaborative Project -3a6355faa0eacfc56e0f43d7752d6610127c4a344765589fb9d611b6ef91c754 +77d8126ac028a559c8f536fe52d304e621bab45533b23617f3c8aec2987e6fb7
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