From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kai Huang Subject: [PATCH 01/10] x86: add SGX Launch Control definition to cpufeature Date: Mon, 8 May 2017 17:24:24 +1200 Message-ID: <20170508052434.3627-2-kai.huang@linux.intel.com> References: <20170508052434.3627-1-kai.huang@linux.intel.com> To: pbonzini@redhat.com, rkrcmar@redhat.com, kvm@vger.kernel.org Return-path: Received: from mail-pf0-f194.google.com ([209.85.192.194]:36198 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751179AbdEHFYw (ORCPT ); Mon, 8 May 2017 01:24:52 -0400 Received: by mail-pf0-f194.google.com with SMTP id v14so8400503pfd.3 for ; Sun, 07 May 2017 22:24:52 -0700 (PDT) In-Reply-To: <20170508052434.3627-1-kai.huang@linux.intel.com> Sender: kvm-owner@vger.kernel.org List-ID: For Intel CPU that supports SGX Launch Control, CPUID.0x7.0:ECX[bit 30] reports the availability of 1-setting of bit 17 of IA32_FEATURE_CONTROL MSR, which enables runtime configuration of SGX Launch Control via IA32_SGXLEPUBKEYHASHn. Signed-off-by: Kai Huang --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 61eba9423b5c..e31c06ac3c65 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -292,6 +292,7 @@ #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ #define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ +#define X86_FEATURE_SGX_LAUNCH_CONTROL (16*32+30) /* SGX Launch Control */ /* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */ #define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */ -- 2.11.0