From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Liu, Yi L" Subject: Re: [Qemu-devel] [RFC PATCH 03/20] intel_iommu: add "svm" option Date: Mon, 8 May 2017 16:15:48 +0800 Message-ID: <20170508081548.GC2931@gmail.com> References: <1493201210-14357-1-git-send-email-yi.l.liu@linux.intel.com> <1493201210-14357-4-git-send-email-yi.l.liu@linux.intel.com> <20170427105317.GE1542@pxdev.xzpeter.org> <20170508112034.GE2820@pxdev.xzpeter.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20170508112034.GE2820-QJIicYCqamqhazCxEpVPD9i2O/JbrIOy@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Peter Xu Cc: "Lan, Tianyu" , "Tian, Kevin" , "kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "jasowang-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org" , "qemu-devel-qX2TKyscuCcdnm+yROfE0A@public.gmane.org" , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , "Pan, Jacob jun" List-Id: iommu@lists.linux-foundation.org T24gTW9uLCBNYXkgMDgsIDIwMTcgYXQgMDc6MjA6MzRQTSArMDgwMCwgUGV0ZXIgWHUgd3JvdGU6 Cj4gT24gTW9uLCBNYXkgMDgsIDIwMTcgYXQgMTA6Mzg6MDlBTSArMDAwMCwgTGl1LCBZaSBMIHdy b3RlOgo+ID4gT24gVGh1LCAyNyBBcHIgMjAxNyAxODo1MzoxNyArMDgwMAo+ID4gUGV0ZXIgWHUg PHBldGVyeEByZWRoYXQuY29tPiB3cm90ZToKPiA+IAo+ID4gPiBPbiBXZWQsIEFwciAyNiwgMjAx NyBhdCAwNjowNjozM1BNICswODAwLCBMaXUsIFlpIEwgd3JvdGU6Cj4gPiA+ID4gRXhwb3NlICJT aGFyZWQgVmlydHVhbCBNZW1vcnkiIHRvIGd1ZXN0IGJ5IHVzaW5nICJzdm0iIG9wdGlvbi4KPiA+ ID4gPiBBbHNvIHVzZSAic3ZtIiB0byBleHBvc2UgU1ZNIHJlbGF0ZWQgY2FwYWJpbGl0aWVzIHRv IGd1ZXN0Lgo+ID4gPiA+IGUuZy4gIi1kZXZpY2UgaW50ZWwtaW9tbXUsIHN2bT1vbiIKPiA+ID4g Pgo+ID4gPiA+IFNpZ25lZC1vZmYtYnk6IExpdSwgWWkgTCA8eWkubC5saXVAbGludXguaW50ZWwu Y29tPgo+ID4gPiA+IC0tLQo+ID4gPiA+ICBody9pMzg2L2ludGVsX2lvbW11LmMgICAgICAgICAg fCAxMCArKysrKysrKysrCj4gPiA+ID4gIGh3L2kzODYvaW50ZWxfaW9tbXVfaW50ZXJuYWwuaCB8 ICA1ICsrKysrCj4gPiA+ID4gaW5jbHVkZS9ody9pMzg2L2ludGVsX2lvbW11LmggIHwgIDEgKwo+ ID4gPiA+ICAzIGZpbGVzIGNoYW5nZWQsIDE2IGluc2VydGlvbnMoKykKPiA+ID4gPgo+ID4gPiA+ IGRpZmYgLS1naXQgYS9ody9pMzg2L2ludGVsX2lvbW11LmMgYi9ody9pMzg2L2ludGVsX2lvbW11 LmMgaW5kZXgKPiA+ID4gPiBiZjk4ZmE1Li5iYTFlN2ViIDEwMDY0NAo+ID4gPiA+IC0tLSBhL2h3 L2kzODYvaW50ZWxfaW9tbXUuYwo+ID4gPiA+ICsrKyBiL2h3L2kzODYvaW50ZWxfaW9tbXUuYwo+ ID4gPiA+IEBAIC0yNDUzLDYgKzI0NTMsNyBAQCBzdGF0aWMgUHJvcGVydHkgdnRkX3Byb3BlcnRp ZXNbXSA9IHsKPiA+ID4gPiAgICAgIERFRklORV9QUk9QX0JPT0woIngtYnVnZ3ktZWltIiwgSW50 ZWxJT01NVVN0YXRlLCBidWdneV9laW0sIGZhbHNlKSwKPiA+ID4gPiAgICAgIERFRklORV9QUk9Q X0JPT0woImNhY2hpbmctbW9kZSIsIEludGVsSU9NTVVTdGF0ZSwgY2FjaGluZ19tb2RlLAo+ID4g PiBGQUxTRSksCj4gPiA+ID4gICAgICBERUZJTkVfUFJPUF9CT09MKCJlY3MiLCBJbnRlbElPTU1V U3RhdGUsIGVjcywgRkFMU0UpLAo+ID4gPiA+ICsgICAgREVGSU5FX1BST1BfQk9PTCgic3ZtIiwg SW50ZWxJT01NVVN0YXRlLCBzdm0sIEZBTFNFKSwKPiA+ID4gPiAgICAgIERFRklORV9QUk9QX0VO RF9PRl9MSVNUKCksCj4gPiA+ID4gIH07Cj4gPiA+ID4KPiA+ID4gPiBAQCAtMjk3Myw2ICsyOTc0 LDE1IEBAIHN0YXRpYyB2b2lkIHZ0ZF9pbml0KEludGVsSU9NTVVTdGF0ZSAqcykKPiA+ID4gPiAg ICAgICAgICBzLT5lY2FwIHw9IFZURF9FQ0FQX0VDUzsKPiA+ID4gPiAgICAgIH0KPiA+ID4gPgo+ ID4gPiA+ICsgICAgaWYgKHMtPnN2bSkgewo+ID4gPiA+ICsgICAgICAgIGlmICghcy0+ZWNzIHx8 ICF4ODZfaW9tbXUtPnB0X3N1cHBvcnRlZCB8fCAhcy0+Y2FjaGluZ19tb2RlKSB7Cj4gPiA+ID4g KyAgICAgICAgICAgIGVycm9yX3JlcG9ydCgiTmVlZCB0byBzZXQgZWNzLCBwdCwgY2FjaGluZy1t b2RlIGZvciBzdm0iKTsKPiA+ID4gPiArICAgICAgICAgICAgZXhpdCgxKTsKPiA+ID4gPiArICAg ICAgICB9Cj4gPiA+ID4gKyAgICAgICAgcy0+Y2FwIHw9IFZURF9DQVBfRFdEIHwgVlREX0NBUF9E UkQ7Cj4gPiA+ID4gKyAgICAgICAgcy0+ZWNhcCB8PSBWVERfRUNBUF9QUlMgfCBWVERfRUNBUF9Q VFMgfCBWVERfRUNBUF9QQVNJRDI4Owo+ID4gPiA+ICsgICAgfQo+ID4gPiA+ICsKPiA+ID4gPiAg ICAgIGlmIChzLT5jYWNoaW5nX21vZGUpIHsKPiA+ID4gPiAgICAgICAgICBzLT5jYXAgfD0gVlRE X0NBUF9DTTsKPiA+ID4gPiAgICAgIH0KPiA+ID4gPiBkaWZmIC0tZ2l0IGEvaHcvaTM4Ni9pbnRl bF9pb21tdV9pbnRlcm5hbC5oCj4gPiA+ID4gYi9ody9pMzg2L2ludGVsX2lvbW11X2ludGVybmFs LmggaW5kZXggNzFhMWMxZS4uZjJhN2QxMiAxMDA2NDQKPiA+ID4gPiAtLS0gYS9ody9pMzg2L2lu dGVsX2lvbW11X2ludGVybmFsLmgKPiA+ID4gPiArKysgYi9ody9pMzg2L2ludGVsX2lvbW11X2lu dGVybmFsLmgKPiA+ID4gPiBAQCAtMTkxLDYgKzE5MSw5IEBACj4gPiA+ID4gICNkZWZpbmUgVlRE X0VDQVBfUFQgICAgICAgICAgICAgICAgICgxVUxMIDw8IDYpCj4gPiA+ID4gICNkZWZpbmUgVlRE X0VDQVBfTUhNViAgICAgICAgICAgICAgICgxNVVMTCA8PCAyMCkKPiA+ID4gPiAgI2RlZmluZSBW VERfRUNBUF9FQ1MgICAgICAgICAgICAgICAgKDFVTEwgPDwgMjQpCj4gPiA+ID4gKyNkZWZpbmUg VlREX0VDQVBfUEFTSUQyOCAgICAgICAgICAgICgxVUxMIDw8IDI4KQo+ID4gPiAKPiA+ID4gQ291 bGQgSSBhc2sgd2hhdCdzIHRoaXMgYml0PyBPbiBteSBzcGVjLCBpdCBzYXlzIHRoaXMgYml0IGlz IHJlc2VydmVkIGFuZCBkZWZ1bmN0IChzcGVjCj4gPiA+IHZlcnNpb246IEp1bmUgMjAxNikuCj4g PiAKPiA+IEFzIEFzaG9rIGNvbmZpcm1lZCwgeWVzIGl0IHNob3VsZCBiZSBiaXQgNDAuIHdvdWxk IHVwZGF0ZSBpdC4KPiAKPiBPay4KPiAKPiA+IAo+ID4gPiA+ICsjZGVmaW5lIFZURF9FQ0FQX1BS UyAgICAgICAgICAgICAgICAoMVVMTCA8PCAyOSkKPiA+ID4gPiArI2RlZmluZSBWVERfRUNBUF9Q VFMgICAgICAgICAgICAgICAgKDB4ZVVMTCA8PCAzNSkKPiA+ID4gCj4gPiA+IFdvdWxkIGl0IGJl dHRlciB3ZSBhdm9pZCB1c2luZyAweGUgaGVyZSwgb3IgYXQgbGVhc3QgYWRkIHNvbWUgY29tbWVu dD8KPiA+IAo+ID4gRm9yIHRoaXMgdmFsdWUsIGl0IG11c3QgYmUgbm8gbW9yZSB0aGFuIHRoZSBi aXRzIGhvc3Qgc3VwcG9ydHMuIFNvIGl0IG1heSBiZQo+ID4gYmV0dGVyIHRvIGhhdmUgYSBkZWZh dWx0IHZhbHVlIGFuZCBtZWFud2hpbGUgZXhwb3NlIGFuIG9wdGlvbiB0byBsZXQgdXNlcgo+ID4g c2V0IGl0LiBob3cgYWJvdXQgeW91ciBvcGluaW9uPwo+IAo+IEkgdGhpbmsgYSBtb3JlIGltcG9y dGFudCBwb2ludCBpcyB0aGF0IHdlIG5lZWQgdG8gbWFrZSBzdXJlIHRoaXMgdmFsdWUKPiBpcyBu byBsYXJnZXIgdGhhbiBoYXJkd2FyZSBzdXBwb3J0PyAKCkFncmVlLiBJZiBpdCBpcyBsYXJnZXIs IHNhbml0eSBjaGVjayB3b3VsZCBmYWlsLgoKPiBTaW5jZSB5b3UgYXJlIGFsc28gd29ya2luZyBv biB0aGUKPiB2ZmlvIGludGVyZmFjZSBmb3IgdmlydC1zdm0uLi4gd291bGQgaXQgYmUgcG9zc2li bGUgdGhhdCB3ZSBjYW4gdGFsawo+IHRvIGtlcm5lbCBpbiBzb21lIHdheSBzbyB0aGF0IHdlIGNh biBrbm93IHRoZSBzdXBwb3J0ZWQgcGFzaWQgc2l6ZSBpbgo+IGhvc3QgSU9NTVU/IFNvIHRoYXQg d2hlbiBndWVzdCBzcGVjaWZpZXMgc29tZXRoaW5nIGJpZ2dlciwgd2UgY2FuIHN0b3AKPiB0aGUg dXNlci4KCklmIGl0IGlzIGp1c3QgdG8gc3RvcCB3aGVuIHRoZSBzaXplIGlzIG5vdCB2YWxpZCwg SSB0aGluayB3ZSBhbHJlYWR5IGhhdmUKc3VjaCBzYW5pdHkgY2hlY2sgaW4gaG9zdCB3aGVuIHRy eWluZyB0byBiaW5kIGd1ZXN0IHBhc2lkIHRhYmxlLiBOb3Qgc3VyZQppZiBpdCBpcyBwcmFjdGlj YWwgdG8gdGFsayB3aXRoIGtlcm5lbCBvbiB0aGUgc3VwcG9ydGVkIHBhc2lkIHNpemUuIEJ1dApt YXkgdGhpbmsgYWJvdXQgaXQuIEl0IGlzIHZlcnkgbGlrZWx5IHRoYXQgd2UgbmVlZCB0byBkbyBp dCB0aHJvdWdoIFZGSU8uCgo+IAo+IEkgZG9uJ3Qga25vdyB0aGUgcHJhY3RpY2FsIHZhbHVlIGZv ciB0aGlzIGZpZWxkLCBpZiBpdCdzIHN0YXRpYwo+IGVub3VnaCwgSSB0aGluayBpdCdzIGFsc28g b2theSB3ZSBtYWtlIGl0IHN0YXRpYyBoZXJlIGFzIHdlbGwuIEJ1dAo+IGFnYWluLCBJIHdvdWxk IHByZWZlciBhdCBsZWFzdCBzb21lIGNvbW1lbnQsIGxpa2U6Cj4gCj4gICAvKiBWYWx1ZSBOIGlu ZGljYXRlcyBQQVNJRCBmaWVsZCBvZiBOKzEgYml0cywgaGVyZSAweGUgc3RhbmRzIGZvci4uICov Cgp5ZXMsIGF0IGxlYXN0IHdlIG5lZWQgdG8gYWRkIHN1Y2ggY29tbWVudHMuIFdvdWxkIGFkZCBp dC4KCj4gPiAKPiA+ID4gCj4gPiA+ID4KPiA+ID4gPiAgLyogQ0FQX1JFRyAqLwo+ID4gPiA+ICAv KiAob2Zmc2V0ID4+IDQpIDw8IDI0ICovCj4gPiA+ID4gQEAgLTIwNyw2ICsyMTAsOCBAQAo+ID4g PiA+ICAjZGVmaW5lIFZURF9DQVBfUFNJICAgICAgICAgICAgICAgICAoMVVMTCA8PCAzOSkKPiA+ ID4gPiAgI2RlZmluZSBWVERfQ0FQX1NMTFBTICAgICAgICAgICAgICAgKCgxVUxMIDw8IDM0KSB8 ICgxVUxMIDw8IDM1KSkKPiA+ID4gPiAgI2RlZmluZSBWVERfQ0FQX0NNICAgICAgICAgICAgICAg ICAgKDFVTEwgPDwgNykKPiA+ID4gPiArI2RlZmluZSBWVERfQ0FQX0RXRCAgICAgICAgICAgICAg ICAgKDFVTEwgPDwgNTQpCj4gPiA+ID4gKyNkZWZpbmUgVlREX0NBUF9EUkQgICAgICAgICAgICAg ICAgICgxVUxMIDw8IDU1KQo+ID4gPiAKPiA+ID4gSnVzdCB0byBjb25maXJtOiBhZnRlciB0aGlz IHNlcmllcywgd2Ugc2hvdWxkIHN1cHBvcnQgZHJhaW4gcmVhZC93cml0ZSB0aGVuLCByaWdodD8K PiA+IAo+ID4gSSBoYXZlbuKAmXQgZG9uZSBzcGVjaWFsIHByb2Nlc3MgYWdhaW5zdCBpdCBpbiBJ T01NVSBlbXVsYXRvci4gSXQncyBzZXQgdG8ga2VlcAo+ID4gY29uc2lzdGVuY2Ugd2l0aCBWVC1k IHNwZWMgc2luY2UgRFdEIGFuZCBEUlcgaXMgcmVxdWlyZWQgY2FwYWJpbGl0eSB3aGVuCj4gPiBQ QVNJRCBpdCByZXBvcnRlZCBhcyBTZXQuIEhvd2V2ZXIsIEkgdGhpbmsgaXQgc2hvdWxkIGJlIGZp bmUgaWYgZ3Vlc3QgaXNzdWUgUUkKPiA+IHdpdGggZHJhaW4gcmVhZC93cml0ZSBzZXQgaW4gdGhl IGRlc2NyaXB0b3IuIEhvc3Qgc2hvdWxkIGJlIGFibGUgdG8gcHJvY2VzcyBpdC4KPiAKPiBJIHNl ZS4gSUlVQyB0aGUgcG9pbnQgaGVyZSBpcyB3ZSBuZWVkIHRvIGRlbGl2ZXIgdGhlc2UgcmVxdWVz dHMgdG8KPiBob3N0IElPTU1VLCBhbmQgSSBndWVzcyB3ZSBuZWVkIHRvIGJlIGFibGUgdG8gZG8g dGhpcyBpbiBhIHN5bmNocm9ub3VzCj4gd2F5IGFzIHdlbGwuCgp5ZXMsIGRlbGl2ZXIgcmVxdWVz dCB0byBob3N0LiBGb3IgYXNzaWduZWQgZGV2aWNlcywgaXQgaXMgb2suIEJUVy4gZG8geW91CnRo aW5rIHdlIG5lZWQgdG8gY29uc2lkZXIgaXQgZm9yIGVtdWxhdGVkIGRldmljZXM/CgpUaGFua3Ms CllpIEwKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmlv bW11IG1haWxpbmcgbGlzdAppb21tdUBsaXN0cy5saW51eC1mb3VuZGF0aW9uLm9yZwpodHRwczov L2xpc3RzLmxpbnV4Zm91bmRhdGlvbi5vcmcvbWFpbG1hbi9saXN0aW5mby9pb21tdQ== From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50373) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d80Z7-0006P9-0J for qemu-devel@nongnu.org; Tue, 09 May 2017 04:32:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d80Z3-0004UL-0y for qemu-devel@nongnu.org; Tue, 09 May 2017 04:32:17 -0400 Received: from mga09.intel.com ([134.134.136.24]:57330) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1d80Z2-0004Sm-Mk for qemu-devel@nongnu.org; Tue, 09 May 2017 04:32:12 -0400 Date: Mon, 8 May 2017 16:15:48 +0800 From: "Liu, Yi L" Message-ID: <20170508081548.GC2931@gmail.com> References: <1493201210-14357-1-git-send-email-yi.l.liu@linux.intel.com> <1493201210-14357-4-git-send-email-yi.l.liu@linux.intel.com> <20170427105317.GE1542@pxdev.xzpeter.org> <20170508112034.GE2820@pxdev.xzpeter.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170508112034.GE2820@pxdev.xzpeter.org> Subject: Re: [Qemu-devel] [RFC PATCH 03/20] intel_iommu: add "svm" option List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Xu Cc: "Liu, Yi L" , "Lan, Tianyu" , "Tian, Kevin" , "Raj, Ashok" , "kvm@vger.kernel.org" , "jean-philippe.brucker@arm.com" , "jasowang@redhat.com" , "iommu@lists.linux-foundation.org" , "qemu-devel@nongnu.org" , "alex.williamson@redhat.com" , "Pan, Jacob jun" On Mon, May 08, 2017 at 07:20:34PM +0800, Peter Xu wrote: > On Mon, May 08, 2017 at 10:38:09AM +0000, Liu, Yi L wrote: > > On Thu, 27 Apr 2017 18:53:17 +0800 > > Peter Xu wrote: > > > > > On Wed, Apr 26, 2017 at 06:06:33PM +0800, Liu, Yi L wrote: > > > > Expose "Shared Virtual Memory" to guest by using "svm" option. > > > > Also use "svm" to expose SVM related capabilities to guest. > > > > e.g. "-device intel-iommu, svm=on" > > > > > > > > Signed-off-by: Liu, Yi L > > > > --- > > > > hw/i386/intel_iommu.c | 10 ++++++++++ > > > > hw/i386/intel_iommu_internal.h | 5 +++++ > > > > include/hw/i386/intel_iommu.h | 1 + > > > > 3 files changed, 16 insertions(+) > > > > > > > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index > > > > bf98fa5..ba1e7eb 100644 > > > > --- a/hw/i386/intel_iommu.c > > > > +++ b/hw/i386/intel_iommu.c > > > > @@ -2453,6 +2453,7 @@ static Property vtd_properties[] = { > > > > DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false), > > > > DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, > > > FALSE), > > > > DEFINE_PROP_BOOL("ecs", IntelIOMMUState, ecs, FALSE), > > > > + DEFINE_PROP_BOOL("svm", IntelIOMMUState, svm, FALSE), > > > > DEFINE_PROP_END_OF_LIST(), > > > > }; > > > > > > > > @@ -2973,6 +2974,15 @@ static void vtd_init(IntelIOMMUState *s) > > > > s->ecap |= VTD_ECAP_ECS; > > > > } > > > > > > > > + if (s->svm) { > > > > + if (!s->ecs || !x86_iommu->pt_supported || !s->caching_mode) { > > > > + error_report("Need to set ecs, pt, caching-mode for svm"); > > > > + exit(1); > > > > + } > > > > + s->cap |= VTD_CAP_DWD | VTD_CAP_DRD; > > > > + s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PTS | VTD_ECAP_PASID28; > > > > + } > > > > + > > > > if (s->caching_mode) { > > > > s->cap |= VTD_CAP_CM; > > > > } > > > > diff --git a/hw/i386/intel_iommu_internal.h > > > > b/hw/i386/intel_iommu_internal.h index 71a1c1e..f2a7d12 100644 > > > > --- a/hw/i386/intel_iommu_internal.h > > > > +++ b/hw/i386/intel_iommu_internal.h > > > > @@ -191,6 +191,9 @@ > > > > #define VTD_ECAP_PT (1ULL << 6) > > > > #define VTD_ECAP_MHMV (15ULL << 20) > > > > #define VTD_ECAP_ECS (1ULL << 24) > > > > +#define VTD_ECAP_PASID28 (1ULL << 28) > > > > > > Could I ask what's this bit? On my spec, it says this bit is reserved and defunct (spec > > > version: June 2016). > > > > As Ashok confirmed, yes it should be bit 40. would update it. > > Ok. > > > > > > > +#define VTD_ECAP_PRS (1ULL << 29) > > > > +#define VTD_ECAP_PTS (0xeULL << 35) > > > > > > Would it better we avoid using 0xe here, or at least add some comment? > > > > For this value, it must be no more than the bits host supports. So it may be > > better to have a default value and meanwhile expose an option to let user > > set it. how about your opinion? > > I think a more important point is that we need to make sure this value > is no larger than hardware support? Agree. If it is larger, sanity check would fail. > Since you are also working on the > vfio interface for virt-svm... would it be possible that we can talk > to kernel in some way so that we can know the supported pasid size in > host IOMMU? So that when guest specifies something bigger, we can stop > the user. If it is just to stop when the size is not valid, I think we already have such sanity check in host when trying to bind guest pasid table. Not sure if it is practical to talk with kernel on the supported pasid size. But may think about it. It is very likely that we need to do it through VFIO. > > I don't know the practical value for this field, if it's static > enough, I think it's also okay we make it static here as well. But > again, I would prefer at least some comment, like: > > /* Value N indicates PASID field of N+1 bits, here 0xe stands for.. */ yes, at least we need to add such comments. Would add it. > > > > > > > > > > > > > /* CAP_REG */ > > > > /* (offset >> 4) << 24 */ > > > > @@ -207,6 +210,8 @@ > > > > #define VTD_CAP_PSI (1ULL << 39) > > > > #define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35)) > > > > #define VTD_CAP_CM (1ULL << 7) > > > > +#define VTD_CAP_DWD (1ULL << 54) > > > > +#define VTD_CAP_DRD (1ULL << 55) > > > > > > Just to confirm: after this series, we should support drain read/write then, right? > > > > I haven’t done special process against it in IOMMU emulator. It's set to keep > > consistence with VT-d spec since DWD and DRW is required capability when > > PASID it reported as Set. However, I think it should be fine if guest issue QI > > with drain read/write set in the descriptor. Host should be able to process it. > > I see. IIUC the point here is we need to deliver these requests to > host IOMMU, and I guess we need to be able to do this in a synchronous > way as well. yes, deliver request to host. For assigned devices, it is ok. BTW. do you think we need to consider it for emulated devices? Thanks, Yi L