From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 08/17] drm/i915: pass gtt page size to insert_entries
Date: Tue, 16 May 2017 09:29:39 +0100 [thread overview]
Message-ID: <20170516082948.28090-9-matthew.auld@intel.com> (raw)
In-Reply-To: <20170516082948.28090-1-matthew.auld@intel.com>
Expose a page size parameter for insert_entries, this is only relevant
for inserting into the 4lvl ppgtt where we pass the gtt_page_size of the
object.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 32 +++++++++++++++++++++++----
drivers/gpu/drm/i915/i915_gem_gtt.h | 1 +
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 ++-
drivers/gpu/drm/i915/selftests/mock_gtt.c | 1 +
4 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index bc3c63e92c16..3be3cbfb6d28 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -210,7 +210,8 @@ static int ppgtt_bind_vma(struct i915_vma *vma,
pte_flags |= PTE_READ_ONLY;
vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start,
- cache_level, pte_flags);
+ vma->obj->gtt_page_size, cache_level,
+ pte_flags);
return 0;
}
@@ -911,6 +912,7 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
struct sg_table *pages,
u64 start,
+ unsigned int page_size,
enum i915_cache_level cache_level,
u32 unused)
{
@@ -929,6 +931,7 @@ static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
struct sg_table *pages,
u64 start,
+ unsigned int page_size,
enum i915_cache_level cache_level,
u32 unused)
{
@@ -940,9 +943,24 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
};
struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
struct gen8_insert_pte idx = gen8_insert_pte(start);
+ bool (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
+ struct i915_page_directory_pointer *pdp,
+ struct sgt_dma *iter,
+ struct gen8_insert_pte *idx,
+ enum i915_cache_level cache_level);
+
+ /* TODO: turn this into vfunc */
+ switch (page_size) {
+ case I915_GTT_PAGE_SIZE_4K:
+ insert_entries = gen8_ppgtt_insert_pte_entries;
+ break;
+ default:
+ MISSING_CASE(page_size);
+ return;
+ }
- while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++], &iter,
- &idx, cache_level))
+ while (insert_entries(ppgtt, pdps[idx.pml4e++], &iter, &idx,
+ cache_level))
GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
}
@@ -1625,6 +1643,7 @@ static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
struct sg_table *pages,
u64 start,
+ unsigned int page_size,
enum i915_cache_level cache_level,
u32 flags)
{
@@ -2098,6 +2117,7 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm,
static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
struct sg_table *st,
u64 start,
+ unsigned int page_size,
enum i915_cache_level level,
u32 unused)
{
@@ -2145,6 +2165,7 @@ static void gen6_ggtt_insert_page(struct i915_address_space *vm,
static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
struct sg_table *st,
u64 start,
+ unsigned int page_size,
enum i915_cache_level level,
u32 flags)
{
@@ -2229,6 +2250,7 @@ static void i915_ggtt_insert_page(struct i915_address_space *vm,
static void i915_ggtt_insert_entries(struct i915_address_space *vm,
struct sg_table *pages,
u64 start,
+ unsigned int page_size,
enum i915_cache_level cache_level,
u32 unused)
{
@@ -2265,7 +2287,7 @@ static int ggtt_bind_vma(struct i915_vma *vma,
intel_runtime_pm_get(i915);
vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start,
- cache_level, pte_flags);
+ I915_GTT_PAGE_SIZE, cache_level, pte_flags);
intel_runtime_pm_put(i915);
/*
@@ -2320,6 +2342,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
appgtt->base.insert_entries(&appgtt->base,
vma->pages, vma->node.start,
+ I915_GTT_PAGE_SIZE,
cache_level, pte_flags);
}
@@ -2327,6 +2350,7 @@ static int aliasing_gtt_bind_vma(struct i915_vma *vma,
intel_runtime_pm_get(i915);
vma->vm->insert_entries(vma->vm,
vma->pages, vma->node.start,
+ I915_GTT_PAGE_SIZE,
cache_level, pte_flags);
intel_runtime_pm_put(i915);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index f8db231c28aa..5a2a3907d266 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -320,6 +320,7 @@ struct i915_address_space {
void (*insert_entries)(struct i915_address_space *vm,
struct sg_table *st,
u64 start,
+ unsigned int page_size,
enum i915_cache_level cache_level,
u32 flags);
void (*cleanup)(struct i915_address_space *vm);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 50710e3f1caa..259b5e139df1 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -256,7 +256,8 @@ static int lowlevel_hole(struct drm_i915_private *i915,
break;
vm->insert_entries(vm, obj->mm.pages, addr,
- I915_CACHE_NONE, 0);
+ I915_GTT_PAGE_SIZE, I915_CACHE_NONE,
+ 0);
}
count = n;
diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c
index a61309c7cb3e..38532a008387 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c
@@ -35,6 +35,7 @@ static void mock_insert_page(struct i915_address_space *vm,
static void mock_insert_entries(struct i915_address_space *vm,
struct sg_table *st,
u64 start,
+ unsigned int page_size,
enum i915_cache_level level, u32 flags)
{
}
--
2.9.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2017-05-16 8:30 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-16 8:29 [PATCH 00/17] add support for huge-gtt-pages Matthew Auld
2017-05-16 8:29 ` [PATCH 01/17] drm/i915: introduce page_size_mask to dev_info Matthew Auld
2017-05-16 8:29 ` [PATCH 02/17] drm/i915: introduce gtt page size Matthew Auld
2017-05-16 8:41 ` Chris Wilson
2017-05-16 9:59 ` Chris Wilson
2017-05-23 12:42 ` Matthew Auld
2017-05-23 12:54 ` Chris Wilson
2017-05-23 13:57 ` Matthew Auld
2017-05-23 14:30 ` Chris Wilson
2017-05-16 8:29 ` [PATCH 03/17] drm/i915: align the vma start to the " Matthew Auld
2017-05-16 8:40 ` Chris Wilson
2017-05-16 8:29 ` [PATCH 04/17] drm/i915: align 64K objects to 2M Matthew Auld
2017-05-16 8:29 ` [PATCH 05/17] drm/i915: fallback to normal pages on vma insert failure Matthew Auld
2017-05-16 8:39 ` Chris Wilson
2017-05-16 8:29 ` [PATCH 06/17] mm/shmem: expose driver overridable huge option Matthew Auld
2017-05-16 10:02 ` Kirill A. Shutemov
2017-05-16 8:29 ` [PATCH 07/17] drm/i915: request THP for shmem backed objects Matthew Auld
2017-05-16 8:29 ` Matthew Auld
2017-05-16 8:29 ` Matthew Auld [this message]
2017-05-16 8:29 ` [PATCH 09/17] drm/i915: enable IPS bit for 64K pages Matthew Auld
2017-05-16 8:29 ` [PATCH 10/17] drm/i915: support inserting 64K pages into the 48b PPGTT Matthew Auld
2017-05-16 8:29 ` [PATCH 11/17] drm/i915: disable GTT cache for 2M/1G pages Matthew Auld
2017-05-16 10:04 ` Ville Syrjälä
2017-05-16 10:11 ` Chris Wilson
2017-05-16 8:29 ` [PATCH 12/17] drm/i915: support inserting 2M pages into the 48b PPGTT Matthew Auld
2017-05-16 8:29 ` [PATCH 13/17] drm/i915: support inserting 1G " Matthew Auld
2017-05-16 8:29 ` [PATCH 14/17] drm/i915/debugfs: include some gtt_page_size metrics Matthew Auld
2017-05-19 10:48 ` Chris Wilson
2017-05-19 10:51 ` Chris Wilson
2017-05-16 8:29 ` [PATCH 15/17] drm/i915: enable platform support for 64K pages Matthew Auld
2017-05-16 8:29 ` [PATCH 16/17] drm/i915: enable platform support for 2M pages Matthew Auld
2017-05-16 8:29 ` [PATCH 17/17] drm/i915: enable platform support for 1G pages Matthew Auld
2017-05-16 8:49 ` ✓ Fi.CI.BAT: success for add support for huge-gtt-pages Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170516082948.28090-9-matthew.auld@intel.com \
--to=matthew.auld@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.