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From: Anatolij Gustschin <agust@denx.de>
To: joshua.clayton@uniwest.com
Cc: linux-fpga@vger.kernel.org, Alan Tull <atull@kernel.org>,
	Moritz Fischer <moritz.fischer@ettus.com>,
	linux-kernel@vger.kernel.org,
	Joshua Clayton <stillcompiling@gmail.com>
Subject: Re: [PATCH] fpga: Add flag to indicate SPI bitstream is bit-reversed
Date: Thu, 18 May 2017 14:09:06 +0200	[thread overview]
Message-ID: <20170518140906.5854a344@crub> (raw)
In-Reply-To: <1665918.lT4CrqcDtW@jclayton-pc>

Hi Joshua,

On Wed, 17 May 2017 07:47:42 -0700
joshua.clayton@uniwest.com joshua.clayton@uniwest.com wrote:
...
>>  #define FPGA_MGR_ENCRYPTED_BITSTREAM	BIT(2)
>> +#define FPGA_MGR_SPI_BITSTREAM_LSB_FIRST	BIT(3)  
>My  thought here is that  FPGA_MGR_BITSTREAM_LSB_FIRST
>is a bit shorter, adequate, and could do if another upload method
>happened to use LSB first organized data.

OK, I'll change and resubmit.

Thanks,

Anatolij

      parent reply	other threads:[~2017-05-18 12:09 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-20 21:43 [PATCH] fpga: Add flag to indicate SPI bitstream is bit-reversed Anatolij Gustschin
2017-05-17 14:47 ` joshua.clayton
2017-05-17 15:53   ` Anatolij Gustschin
2017-05-18 12:09   ` Anatolij Gustschin [this message]

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