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Date: Sun, 21 May 2017 07:35:21 +0200
From: Lukas Wunner <lukas@wunner.de>
To: "Levy, Amir (Jer)" <amir.jer.levy@intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Andreas Noever <andreas.noever@gmail.com>,
        "Jamet, Michael" <michael.jamet@intel.com>,
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        Andy Lutomirski <luto@kernel.org>,
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        Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 18/24] thunderbolt: Store Thunderbolt generation in the
 switch structure
Message-ID: <20170521053521.GB3003@wunner.de>
References: <20170518143914.60902-1-mika.westerberg@linux.intel.com>
 <20170518143914.60902-19-mika.westerberg@linux.intel.com>
 <20170521044735.GA2948@wunner.de>
 <E607265CB020454880711A6F96C05A030106862644@hasmsx107.ger.corp.intel.com>
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On Sun, May 21, 2017 at 05:29:47AM +0000, Levy, Amir (Jer) wrote:
> On Sun, May 21 2017, 07:47 AM, Lukas Wunner wrote:
> > On Thu, May 18, 2017 at 05:39:08PM +0300, Mika Westerberg wrote:
> > > +
> > > +	default:
> > > +		sw->generation = 1;
> > > +		break;
> > 
> > If someone adds an entry for, say, a new TB3 controller to nhi_ids[] but
> > forgets to update this function, the controller is assigned the wrong
> > generation number.  It might be better to make TB3 the default and list
> > each TB1 controller instead since it's less likely for Intel to introduce
> > an older gen chip.
> > 
> > Generally I think it's problematic to require that multiple files are
> > touched whenever a new controller is added.  Isn't the generation number
> > or link speed (10/20/40) stored in some register in PCI config space
> > (VSEC 0x1234) or TB config space?
> 
> How about setting information, that isn't available from PCI, in
> pci_device_id.driver_data when initializing nhi_ids[]?

Right, that would also be possible, though reading the generation number
from a register would be more elegant, if such a register exists.

Thanks,

Lukas