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From: "Du, Changbin" <changbin.du@intel.com>
To: linux-pci@vger.kernel.org
Cc: changbin.du@intel.com, linux-kernel@vger.kernel.org
Subject: [Q] What about PCI mmio access alignment?
Date: Thu, 25 May 2017 18:12:57 +0800	[thread overview]
Message-ID: <20170525101256.GA12183@intel.com> (raw)

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Hi, guys,
I have a basic quesion about the alignment when access PCI bar mmio space. Is
the address accessed must be DW aligned and count must be DW aligned?

As far as I know, The address field of TLB ignore lower 2 bits and the unit of
length field also is DW. So does it mean above question is Yes? Else will CPU
handle unaligned access for mmio space?

I want to know wether below access illegal or not:
  - readb(bar0)
  - readb(bar0 + 1)
  - readl(bar0)

Thanks,
Changbin Du

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             reply	other threads:[~2017-05-25 10:16 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-25 10:12 Du, Changbin [this message]
2017-05-27 15:32 ` [Q] What about PCI mmio access alignment? Andy Shevchenko
2017-05-28 10:54   ` Du, Changbin

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