From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joerg Roedel Subject: Re: [PATCH 6/7] iommu/arm-smmu-v3: Add support for PCI ATS Date: Tue, 30 May 2017 12:28:31 +0200 Message-ID: <20170530102831.GJ2818@8bytes.org> References: <20170524180143.19855-1-jean-philippe.brucker@arm.com> <20170524180143.19855-7-jean-philippe.brucker@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20170524180143.19855-7-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Jean-Philippe Brucker Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org, hanjun.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, sudeep.holla-5wv7dgnIgG8@public.gmane.org, rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org, lenb-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, robin.murphy-5wv7dgnIgG8@public.gmane.org, okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, sunil.kovvuri-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, tn-nYOzD4b6Jr9Wk0Htik3J/w@public.gmane.org List-Id: linux-acpi@vger.kernel.org On Wed, May 24, 2017 at 07:01:42PM +0100, Jean-Philippe Brucker wrote: > * TLB invalidation by range is batched and committed with a single sync. > Batching ATC invalidation is inconvenient, endpoints limit the number of > inflight invalidations. We'd have to count the number of invalidations > queued and send a sync periodically. In addition, I suspect we always > need a sync between TLB and ATC invalidation for the same page. This sounds like the number of outstanding ATS invalidations is not managed by the SMMU hardware, is that right? Joerg -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: Date: Tue, 30 May 2017 12:28:31 +0200 From: Joerg Roedel To: Jean-Philippe Brucker Subject: Re: [PATCH 6/7] iommu/arm-smmu-v3: Add support for PCI ATS Message-ID: <20170530102831.GJ2818@8bytes.org> References: <20170524180143.19855-1-jean-philippe.brucker@arm.com> <20170524180143.19855-7-jean-philippe.brucker@arm.com> MIME-Version: 1.0 In-Reply-To: <20170524180143.19855-7-jean-philippe.brucker@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org, thunder.leizhen@huawei.com, rjw@rjwysocki.net, will.deacon@arm.com, okaya@codeaurora.org, linux-acpi@vger.kernel.org, iommu@lists.linux-foundation.org, robh+dt@kernel.org, hanjun.guo@linaro.org, sudeep.holla@arm.com, bhelgaas@google.com, tn@semihalf.com, sunil.kovvuri@gmail.com, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org, lenb@kernel.org Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: On Wed, May 24, 2017 at 07:01:42PM +0100, Jean-Philippe Brucker wrote: > * TLB invalidation by range is batched and committed with a single sync. > Batching ATC invalidation is inconvenient, endpoints limit the number of > inflight invalidations. We'd have to count the number of invalidations > queued and send a sync periodically. In addition, I suspect we always > need a sync between TLB and ATC invalidation for the same page. This sounds like the number of outstanding ATS invalidations is not managed by the SMMU hardware, is that right? Joerg _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: joro@8bytes.org (Joerg Roedel) Date: Tue, 30 May 2017 12:28:31 +0200 Subject: [PATCH 6/7] iommu/arm-smmu-v3: Add support for PCI ATS In-Reply-To: <20170524180143.19855-7-jean-philippe.brucker@arm.com> References: <20170524180143.19855-1-jean-philippe.brucker@arm.com> <20170524180143.19855-7-jean-philippe.brucker@arm.com> Message-ID: <20170530102831.GJ2818@8bytes.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, May 24, 2017 at 07:01:42PM +0100, Jean-Philippe Brucker wrote: > * TLB invalidation by range is batched and committed with a single sync. > Batching ATC invalidation is inconvenient, endpoints limit the number of > inflight invalidations. We'd have to count the number of invalidations > queued and send a sync periodically. In addition, I suspect we always > need a sync between TLB and ATC invalidation for the same page. This sounds like the number of outstanding ATS invalidations is not managed by the SMMU hardware, is that right? Joerg