From mboxrd@z Thu Jan 1 00:00:00 1970 From: Patrick Wildt Date: Thu, 1 Jun 2017 16:04:49 +0200 Subject: [U-Boot] [PATCH] arm: sunxi: initial support for NanoPi Neo2 In-Reply-To: <20170601125726.GJ10782@bill-the-cat> References: <20170509124341.GA5304@eris.local> <7ca52b2f-c0d8-5916-9330-7252c20e0097@suse.de> <20170601124503.GA37963@eris.local> <20170601125726.GJ10782@bill-the-cat> Message-ID: <20170601140448.GA38166@eris.local> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de On Thu, Jun 01, 2017 at 08:57:26AM -0400, Tom Rini wrote: > On Thu, Jun 01, 2017 at 02:45:03PM +0200, Patrick Wildt wrote: > > On Wed, May 24, 2017 at 01:44:26PM +0100, Andre Przywara wrote: > > > Hi, > > >=20 > > > On 24/05/17 12:50, Andreas F=C3=A4rber wrote: > > > > Hej Patrick, > > > >=20 > > > > Am 09.05.2017 um 14:43 schrieb Patrick Wildt: > > > >> The NanoPi Neo2 is basically the same as the NanoPi Neo, but that = they > > > >> replaced the SoC with the 64-bit Allwinner H5 SoC. Add a (64-bit = only) > > > >> defconfig defining the required options to build the U-Boot proper. > > > >> > > > >> Create a new .dts file for it by including the (32-bit) H3 SoC .dt= si > > > >> and changing the differing components accordingly, like it's been > > > >> done for the OrangePi PC 2. > > > >> > > > >> Signed-off-by: Patrick Wildt > > > >=20 > > > > I've tested this patch on top of yesterday's master branch > > > > (4c78028737c3185f49f5691183aeac3478b5f699 "mksunxi_fit_atf.sh: Allo= w for > > > > this to complete when bl31.bin is missing"). > > > >=20 > > > > Considering Tom's unanswered question, is there any diff to the ups= tream > > > > kernel .dts? Expected would be to just copy the Linux .dts file her= e and > > > > to state which tree and commit/tag it was taken from. > >=20 > > I mailed Tom in private asking what to explictly state since 90% was > > from u-boot and 10% from Linux-Sunxi (not mainline). I didn't get a > > reply, so there was no further mail from me. > >=20 > > So should I pull it now from v4.12-rc2? >=20 > Sorry. I'm trying to help make sure dts changes are on their way to the > mainline Linux kernel, so that we don't get out of sync. So, does > v4.12-rc2 have everything you need? Thanks! >=20 > --=20 > Tom There's even v4.12-rc3 now. It does not have the NanoPi Neo2, but I guess as a start one should do a sync for the rest of the stuff. What's holding us up from using the Linux device trees without any changes? This diff I attach inline copies all a64, h3 and h5 related files from v4.12-rc3 (so, mainline) and modifies the emac driver to use the new pinmux attributes. Copied from 5ed02dbb497422bf225783f46e6eadd237d23d6b, v4.12-rc3. Opinions? Patrick diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i= -a64-bananapi-m64.dts index 02db114..6872135 100644 --- a/arch/arm/dts/sun50i-a64-bananapi-m64.dts +++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts @@ -1,6 +1,5 @@ /* * Copyright (c) 2016 ARM Ltd. - * Copyright (C) 2017 Jagan Teki * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-= h5-orangepi-pc2.dts index de60f78..dfecc17 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts @@ -1,17 +1,17 @@ /* - * Copyright (c) 2016 ARM Ltd. + * Copyright (C) 2016 ARM Ltd. * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * - * a) This library is free software; you can redistribute it and/or + * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * - * This library is distributed in the hope that it will be useful, + * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. @@ -41,107 +41,148 @@ */ =20 /dts-v1/; +#include "sun50i-h5.dtsi" =20 -#include "sun8i-h3.dtsi" +#include +#include +#include =20 / { - model =3D "OrangePi PC 2"; - compatible =3D "xunlong,orangepi-pc-2", "allwinner,sun50i-h5"; - - cpus { - cpu at 0 { - compatible =3D "arm,cortex-a53", "arm,armv8"; - enable-method =3D "psci"; - }; - cpu at 1 { - compatible =3D "arm,cortex-a53", "arm,armv8"; - enable-method =3D "psci"; - }; - cpu at 2 { - compatible =3D "arm,cortex-a53", "arm,armv8"; - enable-method =3D "psci"; - }; - cpu at 3 { - compatible =3D "arm,cortex-a53", "arm,armv8"; - enable-method =3D "psci"; - }; - }; - - psci { - compatible =3D "arm,psci-0.2"; - method =3D "smc"; + model =3D "Xunlong Orange Pi PC 2"; + compatible =3D "xunlong,orangepi-pc2", "allwinner,sun50i-h5"; + + reg_vcc3v3: vcc3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; }; =20 - timer { - compatible =3D "arm,armv8-timer"; + aliases { + serial0 =3D &uart0; }; =20 chosen { stdout-path =3D "serial0:115200n8"; }; =20 - memory { - reg =3D <0x40000000 0x40000000>; - }; + leds { + compatible =3D "gpio-leds"; =20 - aliases { - serial0 =3D &uart0; - ethernet0 =3D &emac; + pwr { + label =3D "orangepi:green:pwr"; + gpios =3D <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state =3D "on"; + }; + + status { + label =3D "orangepi:red:status"; + gpios =3D <&pio 0 20 GPIO_ACTIVE_HIGH>; + }; }; =20 - soc { - reg_vcc3v3: vcc3v3 { - compatible =3D "regulator-fixed"; - regulator-name =3D "vcc3v3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; + r-gpio-keys { + compatible =3D "gpio-keys"; + + sw4 { + label =3D "sw4"; + linux,code =3D ; + gpios =3D <&r_pio 0 3 GPIO_ACTIVE_LOW>; }; }; + + reg_usb0_vbus: usb0-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb0-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status =3D "okay"; + }; +}; + +&codec { + allwinner,audio-routing =3D + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status =3D "okay"; +}; + +&ehci0 { + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&ehci2 { + status =3D "okay"; +}; + +&ehci3 { + status =3D "okay"; }; =20 -&gic { - compatible =3D "arm,gic-400"; +&ir { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ir_pins_a>; + status =3D "okay"; }; =20 &mmc0 { - compatible =3D "allwinner,sun50i-h5-mmc", - "allwinner,sun50i-a64-mmc", - "allwinner,sun5i-a13-mmc"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply =3D <®_vcc3v3>; bus-width =3D <4>; - cd-gpios =3D <&pio 5 6 0>; - cd-inverted; + cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status =3D "okay"; }; =20 -&uart0 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&uart0_pins_a>; +&ohci0 { status =3D "okay"; }; =20 -&usbphy { +&ohci1 { status =3D "okay"; }; =20 -&ohci1 { +&ohci2 { status =3D "okay"; }; =20 -&ehci1 { +&ohci3 { status =3D "okay"; }; =20 -&emac { +&uart0 { pinctrl-names =3D "default"; - pinctrl-0 =3D <&emac_rgmii_pins>; - phy-mode =3D "rgmii"; - phy =3D <&phy1>; + pinctrl-0 =3D <&uart0_pins_a>; status =3D "okay"; +}; =20 - phy1: ethernet-phy at 1 { - reg =3D <1>; - }; +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>; + status =3D "disabled"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_pins>; + status =3D "disabled"; +}; + +&usb_otg { + dr_mode =3D "otg"; + status =3D "okay"; +}; + +&usbphy { + /* USB Type-A ports' VBUS is always on */ + usb0_id_det-gpios =3D <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply =3D <®_usb0_vbus>; + status =3D "okay"; }; diff --git a/arch/arm/dts/sun50i-h5.dtsi b/arch/arm/dts/sun50i-h5.dtsi new file mode 100644 index 0000000..4d314a2 --- /dev/null +++ b/arch/arm/dts/sun50i-h5.dtsi @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sunxi-h3-h5.dtsi" + +/ { + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu at 0 { + compatible =3D "arm,cortex-a53", "arm,armv8"; + device_type =3D "cpu"; + reg =3D <0>; + enable-method =3D "psci"; + }; + + cpu at 1 { + compatible =3D "arm,cortex-a53", "arm,armv8"; + device_type =3D "cpu"; + reg =3D <1>; + enable-method =3D "psci"; + }; + + cpu at 2 { + compatible =3D "arm,cortex-a53", "arm,armv8"; + device_type =3D "cpu"; + reg =3D <2>; + enable-method =3D "psci"; + }; + + cpu at 3 { + compatible =3D "arm,cortex-a53", "arm,armv8"; + device_type =3D "cpu"; + reg =3D <3>; + enable-method =3D "psci"; + }; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; + +&ccu { + compatible =3D "allwinner,sun50i-h5-ccu"; +}; + +&mmc0 { + compatible =3D "allwinner,sun50i-h5-mmc", + "allwinner,sun50i-a64-mmc"; + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names =3D "ahb", "mmc"; +}; + +&mmc1 { + compatible =3D "allwinner,sun50i-h5-mmc", + "allwinner,sun50i-a64-mmc"; + clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names =3D "ahb", "mmc"; +}; + +&mmc2 { + compatible =3D "allwinner,sun50i-h5-emmc", + "allwinner,sun50i-a64-emmc"; + clocks =3D <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names =3D "ahb", "mmc"; +}; + +&pio { + compatible =3D "allwinner,sun50i-h5-pinctrl"; +}; diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/su= n8i-h2-plus-orangepi-zero.dts index 20d489c..9e8b082 100644 --- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts @@ -49,7 +49,6 @@ =20 #include #include -#include =20 / { model =3D "Xunlong Orange Pi Zero"; @@ -92,22 +91,16 @@ wifi_pwrseq: wifi_pwrseq { compatible =3D "mmc-pwrseq-simple"; reset-gpios =3D <&r_pio 0 7 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms =3D <200>; }; }; =20 -&ehci1 { +&ehci0 { status =3D "okay"; }; =20 -&emac { - phy =3D <&phy1>; - phy-mode =3D "mii"; - allwinner,use-internal-phy; - allwinner,leds-active-low; +&ehci1 { status =3D "okay"; - phy1: ethernet-phy at 1 { - reg =3D <1>; - }; }; =20 &mmc0 { @@ -138,6 +131,14 @@ }; }; =20 +&mmc1_pins_a { + bias-pull-up; +}; + +&ohci0 { + status =3D "okay"; +}; + &ohci1 { status =3D "okay"; }; @@ -148,7 +149,29 @@ status =3D "okay"; }; =20 +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>; + status =3D "disabled"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_pins>; + status =3D "disabled"; +}; + +&usb_otg { + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + &usbphy { - /* USB VBUS is always on */ + /* + * USB Type-A port VBUS is always on. However, MicroUSB VBUS can only + * power up the board; when it's used as OTG port, this VBUS is + * always off even if the board is powered via GPIO pins. + */ status =3D "okay"; + usb0_id_det-gpios =3D <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ }; diff --git a/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/dts/sun8= i-h3-bananapi-m2-plus.dts index f3b1d5f..52acbe1 100644 --- a/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts @@ -46,7 +46,6 @@ =20 #include #include -#include =20 / { model =3D "Banana Pi BPI-M2-Plus"; @@ -156,24 +155,18 @@ =20 &r_pio { pwr_led_bpi_m2p: led_pins at 0 { - allwinner,pins =3D "PL10"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PL10"; + function =3D "gpio_out"; }; =20 sw_r_bpi_m2p: key_pins at 0 { - allwinner,pins =3D "PL3"; - allwinner,function =3D "gpio_in"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PL3"; + function =3D "gpio_in"; }; =20 wifi_en_bpi_m2p: wifi_en_pin { - allwinner,pins =3D "PL7"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PL7"; + function =3D "gpio_out"; }; }; =20 @@ -185,7 +178,7 @@ =20 &uart1 { pinctrl-names =3D "default"; - pinctrl-0 =3D <&uart1_pins_a>; + pinctrl-0 =3D <&uart1_pins>, <&uart1_rts_cts_pins>; status =3D "okay"; }; =20 diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-= h3-nanopi-neo-air.dts index 3ba081c..03ff6f8 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi" =20 #include -#include =20 / { model =3D "FriendlyARM NanoPi NEO Air"; diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/dts/sun8i-h3-n= anopi-neo.dts index 5113059..8d2cc6e 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-neo.dts @@ -46,14 +46,3 @@ model =3D "FriendlyARM NanoPi NEO"; compatible =3D "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; }; - -&emac { - phy =3D <&phy1>; - phy-mode =3D "mii"; - allwinner,use-internal-phy; - allwinner,leds-active-low; - status =3D "okay"; - phy1: ethernet-phy at 1 { - reg =3D <1>; - }; -}; diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-o= rangepi-2.dts index caa1a69..5b6d145 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts @@ -46,7 +46,6 @@ =20 #include #include -#include =20 / { model =3D "Xunlong Orange Pi 2"; @@ -109,17 +108,6 @@ status =3D "okay"; }; =20 -&emac { - phy =3D <&phy1>; - phy-mode =3D "mii"; - allwinner,use-internal-phy; - allwinner,leds-active-low; - status =3D "okay"; - phy1: ethernet-phy at 1 { - reg =3D <1>; - }; -}; - &ir { pinctrl-names =3D "default"; pinctrl-0 =3D <&ir_pins_a>; @@ -156,33 +144,25 @@ =20 &pio { leds_opc: led_pins at 0 { - allwinner,pins =3D "PA15"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PA15"; + function =3D "gpio_out"; }; }; =20 &r_pio { leds_r_opc: led_pins at 0 { - allwinner,pins =3D "PL10"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PL10"; + function =3D "gpio_out"; }; =20 sw_r_opc: key_pins at 0 { - allwinner,pins =3D "PL3", "PL4"; - allwinner,function =3D "gpio_in"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PL3", "PL4"; + function =3D "gpio_in"; }; =20 wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin at 0 { - allwinner,pins =3D "PL7"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PL7"; + function =3D "gpio_out"; }; }; =20 @@ -197,8 +177,26 @@ status =3D "okay"; }; =20 +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>; + status =3D "disabled"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_pins>; + status =3D "disabled"; +}; + +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart3_pins>; + status =3D "disabled"; +}; + &usb1_vbus_pin_a { - allwinner,pins =3D "PG13"; + pins =3D "PG13"; }; =20 &usbphy { diff --git a/arch/arm/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/dts/sun8i-h= 3-orangepi-lite.dts index 1550fee..9b47a0d 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-lite.dts @@ -46,7 +46,6 @@ =20 #include #include -#include =20 / { model =3D "Xunlong Orange Pi Lite"; @@ -143,26 +142,20 @@ =20 &pio { leds_opc: led_pins at 0 { - allwinner,pins =3D "PA15"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PA15"; + function =3D "gpio_out"; }; }; =20 &r_pio { leds_r_opc: led_pins at 0 { - allwinner,pins =3D "PL10"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PL10"; + function =3D "gpio_out"; }; =20 sw_r_opc: key_pins at 0 { - allwinner,pins =3D "PL3"; - allwinner,function =3D "gpio_in"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PL3"; + function =3D "gpio_in"; }; }; =20 diff --git a/arch/arm/dts/sun8i-h3-orangepi-one.dts b/arch/arm/dts/sun8i-h3= -orangepi-one.dts index 8df5c74..5fea430 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-one.dts @@ -46,7 +46,6 @@ =20 #include #include -#include =20 / { model =3D "Xunlong Orange Pi One"; @@ -90,19 +89,12 @@ }; }; =20 -&ehci1 { +&ehci0 { status =3D "okay"; }; =20 -&emac { - phy =3D <&phy1>; - phy-mode =3D "mii"; - allwinner,use-internal-phy; - allwinner,leds-active-low; +&ehci1 { status =3D "okay"; - phy1: ethernet-phy at 1 { - reg =3D <1>; - }; }; =20 &mmc0 { @@ -115,42 +107,70 @@ status =3D "okay"; }; =20 +&ohci0 { + status =3D "okay"; +}; + &ohci1 { status =3D "okay"; }; =20 &pio { leds_opc: led_pins at 0 { - allwinner,pins =3D "PA15"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PA15"; + function =3D "gpio_out"; }; }; =20 &r_pio { leds_r_opc: led_pins at 0 { - allwinner,pins =3D "PL10"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PL10"; + function =3D "gpio_out"; }; =20 sw_r_opc: key_pins at 0 { - allwinner,pins =3D "PL3"; - allwinner,function =3D "gpio_in"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PL3"; + function =3D "gpio_in"; }; }; =20 +®_usb0_vbus { + gpio =3D <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status =3D "okay"; +}; + &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_pins_a>; status =3D "okay"; }; =20 +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>; + status =3D "disabled"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_pins>; + status =3D "disabled"; +}; + +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart3_pins>; + status =3D "disabled"; +}; + +&usb_otg { + dr_mode =3D "otg"; + status =3D "okay"; +}; + &usbphy { - /* USB VBUS is always on */ + /* USB Type-A port's VBUS is always on */ + usb0_id_det-gpios =3D <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply =3D <®_usb0_vbus>; status =3D "okay"; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/dts/sun8= i-h3-orangepi-pc-plus.dts index 851fd2c..8b93f5c 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts @@ -82,7 +82,7 @@ =20 &mmc2_8bit_pins { /* Increase drive strength for DDR modes */ - allwinner,drive =3D ; + drive-strength =3D <40>; /* eMMC is missing pull-ups */ - allwinner,pull =3D ; + bias-pull-up; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-= orangepi-pc.dts index b8340f7..f148111 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts @@ -46,7 +46,6 @@ =20 #include #include -#include =20 / { model =3D "Xunlong Orange Pi PC"; @@ -90,6 +89,14 @@ }; }; =20 +&codec { + allwinner,audio-routing =3D + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status =3D "okay"; +}; + &ehci1 { status =3D "okay"; }; @@ -132,26 +139,20 @@ =20 &pio { leds_opc: led_pins at 0 { - allwinner,pins =3D "PA15"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PA15"; + function =3D "gpio_out"; }; }; =20 &r_pio { leds_r_opc: led_pins at 0 { - allwinner,pins =3D "PL10"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PL10"; + function =3D "gpio_out"; }; =20 sw_r_opc: key_pins at 0 { - allwinner,pins =3D "PL3"; - allwinner,function =3D "gpio_in"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PL3"; + function =3D "gpio_in"; }; }; =20 @@ -161,18 +162,25 @@ status =3D "okay"; }; =20 -&usbphy { - /* USB VBUS is always on */ - status =3D "okay"; +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>; + status =3D "disabled"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2_pins>; + status =3D "disabled"; +}; + +&uart3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart3_pins>; + status =3D "disabled"; }; =20 -&emac { - phy =3D <&phy1>; - phy-mode =3D "mii"; - allwinner,use-internal-phy; - allwinner,leds-active-low; +&usbphy { + /* USB VBUS is always on */ status =3D "okay"; - phy1: ethernet-phy at 1 { - reg =3D <1>; - }; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/dts/sun8i-h= 3-orangepi-plus.dts index e7079b2..8c40ab7 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-plus.dts @@ -47,18 +47,6 @@ model =3D "Xunlong Orange Pi Plus / Plus 2"; compatible =3D "xunlong,orangepi-plus", "allwinner,sun8i-h3"; =20 - reg_gmac_3v3: gmac-3v3 { - compatible =3D "regulator-fixed"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&gmac_power_pin_orangepi>; - regulator-name =3D "gmac-3v3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - startup-delay-us =3D <100000>; - enable-active-high; - gpio =3D <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - reg_usb3_vbus: usb3-vbus { compatible =3D "regulator-fixed"; pinctrl-names =3D "default"; @@ -76,15 +64,6 @@ status =3D "okay"; }; =20 -&emac { - /* The Orange Pi Plus uses an external phy */ - pinctrl-names =3D "default"; - pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; - phy-mode =3D "rgmii"; - /delete-property/allwinner,use-internal-phy; -}; - &mmc2 { pinctrl-names =3D "default"; pinctrl-0 =3D <&mmc2_8bit_pins>; @@ -97,24 +76,15 @@ =20 &mmc2_8bit_pins { /* Increase drive strength for DDR modes */ - allwinner,drive =3D ; + drive-strength =3D <40>; /* eMMC is missing pull-ups */ - allwinner,pull =3D ; + bias-pull-up; }; =20 &pio { - gmac_power_pin_orangepi: gmac_power_pin at 0 { - allwinner,pins =3D "PD6"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; - }; - usb3_vbus_pin_a: usb3_vbus_pin at 0 { - allwinner,pins =3D "PG11"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; + pins =3D "PG11"; + function =3D "gpio_out"; }; }; =20 diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/dts/sun8i= -h3-orangepi-plus2e.dts index f97b040..5851a47 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts @@ -50,34 +50,4 @@ / { model =3D "Xunlong Orange Pi Plus 2E"; compatible =3D "xunlong,orangepi-plus2e", "allwinner,sun8i-h3"; - - reg_gmac_3v3: gmac-3v3 { - compatible =3D "regulator-fixed"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&gmac_power_pin_orangepi>; - regulator-name =3D "gmac-3v3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - startup-delay-us =3D <100000>; - enable-active-high; - gpio =3D <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&emac { - /* The Orange Pi Plus 2E uses an external gbit phy */ - pinctrl-names =3D "default"; - pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; - phy-mode =3D "rgmii"; - /delete-property/allwinner,use-internal-phy; -}; - -&pio { - gmac_power_pin_orangepi: gmac_power_pin at 0 { - allwinner,pins =3D "PD6"; - allwinner,function =3D "gpio_out"; - allwinner,drive =3D ; - allwinner,pull =3D ; - }; }; diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi index afa6079..b36f9f4 100644 --- a/arch/arm/dts/sun8i-h3.dtsi +++ b/arch/arm/dts/sun8i-h3.dtsi @@ -40,20 +40,9 @@ * OTHER DEALINGS IN THE SOFTWARE. */ =20 -#include "skeleton.dtsi" - -#include -#include -#include -#include +#include "sunxi-h3-h5.dtsi" =20 / { - interrupt-parent =3D <&gic>; - - aliases { - ethernet0 =3D &emac; - }; - cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -90,445 +79,48 @@ , ; }; +}; =20 - clocks { - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - - osc24M: osc24M_clk { - #clock-cells =3D <0>; - compatible =3D "fixed-clock"; - clock-frequency =3D <24000000>; - clock-output-names =3D "osc24M"; - }; - - osc32k: osc32k_clk { - #clock-cells =3D <0>; - compatible =3D "fixed-clock"; - clock-frequency =3D <32768>; - clock-output-names =3D "osc32k"; - }; - - apb0: apb0_clk { - compatible =3D "fixed-factor-clock"; - #clock-cells =3D <0>; - clock-div =3D <1>; - clock-mult =3D <1>; - clocks =3D <&osc24M>; - clock-output-names =3D "apb0"; - }; - - apb0_gates: clk at 01f01428 { - compatible =3D "allwinner,sun8i-h3-apb0-gates-clk", - "allwinner,sun4i-a10-gates-clk"; - reg =3D <0x01f01428 0x4>; - #clock-cells =3D <1>; - clocks =3D <&apb0>; - clock-indices =3D <0>, <1>; - clock-output-names =3D "apb0_pio", "apb0_ir"; - }; - - ir_clk: ir_clk at 01f01454 { - compatible =3D "allwinner,sun4i-a10-mod0-clk"; - reg =3D <0x01f01454 0x4>; - #clock-cells =3D <0>; - clocks =3D <&osc32k>, <&osc24M>; - clock-output-names =3D "ir"; - }; - }; - - soc { - compatible =3D "simple-bus"; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - - syscon: syscon at 01c00000 { - compatible =3D "allwinner,sun8i-h3-syscon","syscon"; - reg =3D <0x01c00000 0x34>; - }; - - dma: dma-controller at 01c02000 { - compatible =3D "allwinner,sun8i-h3-dma"; - reg =3D <0x01c02000 0x1000>; - interrupts =3D ; - clocks =3D <&ccu CLK_BUS_DMA>; - resets =3D <&ccu RST_BUS_DMA>; - #dma-cells =3D <1>; - }; - - mmc0: mmc at 01c0f000 { - compatible =3D "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; - reg =3D <0x01c0f000 0x1000>; - clocks =3D <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names =3D "ahb", - "mmc", - "output", - "sample"; - resets =3D <&ccu RST_BUS_MMC0>; - reset-names =3D "ahb"; - interrupts =3D ; - status =3D "disabled"; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - mmc1: mmc at 01c10000 { - compatible =3D "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; - reg =3D <0x01c10000 0x1000>; - clocks =3D <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names =3D "ahb", - "mmc", - "output", - "sample"; - resets =3D <&ccu RST_BUS_MMC1>; - reset-names =3D "ahb"; - interrupts =3D ; - status =3D "disabled"; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - mmc2: mmc at 01c11000 { - compatible =3D "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; - reg =3D <0x01c11000 0x1000>; - clocks =3D <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names =3D "ahb", - "mmc", - "output", - "sample"; - resets =3D <&ccu RST_BUS_MMC2>; - reset-names =3D "ahb"; - interrupts =3D ; - status =3D "disabled"; - #address-cells =3D <1>; - #size-cells =3D <0>; - }; - - usbphy: phy at 01c19400 { - compatible =3D "allwinner,sun8i-h3-usb-phy"; - reg =3D <0x01c19400 0x2c>, - <0x01c1a800 0x4>, - <0x01c1b800 0x4>, - <0x01c1c800 0x4>, - <0x01c1d800 0x4>; - reg-names =3D "phy_ctrl", - "pmu0", - "pmu1", - "pmu2", - "pmu3"; - clocks =3D <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>, - <&ccu CLK_USB_PHY3>; - clock-names =3D "usb0_phy", - "usb1_phy", - "usb2_phy", - "usb3_phy"; - resets =3D <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>, - <&ccu RST_USB_PHY3>; - reset-names =3D "usb0_reset", - "usb1_reset", - "usb2_reset", - "usb3_reset"; - status =3D "disabled"; - #phy-cells =3D <1>; - }; - - ehci1: usb at 01c1b000 { - compatible =3D "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg =3D <0x01c1b000 0x100>; - interrupts =3D ; - clocks =3D <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; - resets =3D <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; - phys =3D <&usbphy 1>; - phy-names =3D "usb"; - status =3D "disabled"; - }; - - ohci1: usb at 01c1b400 { - compatible =3D "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg =3D <0x01c1b400 0x100>; - interrupts =3D ; - clocks =3D <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets =3D <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; - phys =3D <&usbphy 1>; - phy-names =3D "usb"; - status =3D "disabled"; - }; - - ehci2: usb at 01c1c000 { - compatible =3D "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg =3D <0x01c1c000 0x100>; - interrupts =3D ; - clocks =3D <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; - resets =3D <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; - phys =3D <&usbphy 2>; - phy-names =3D "usb"; - status =3D "disabled"; - }; - - ohci2: usb at 01c1c400 { - compatible =3D "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg =3D <0x01c1c400 0x100>; - interrupts =3D ; - clocks =3D <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_USB_OHCI2>; - resets =3D <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; - phys =3D <&usbphy 2>; - phy-names =3D "usb"; - status =3D "disabled"; - }; - - ehci3: usb at 01c1d000 { - compatible =3D "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg =3D <0x01c1d000 0x100>; - interrupts =3D ; - clocks =3D <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; - resets =3D <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; - phys =3D <&usbphy 3>; - phy-names =3D "usb"; - status =3D "disabled"; - }; - - ohci3: usb at 01c1d400 { - compatible =3D "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg =3D <0x01c1d400 0x100>; - interrupts =3D ; - clocks =3D <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_USB_OHCI3>; - resets =3D <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; - phys =3D <&usbphy 3>; - phy-names =3D "usb"; - status =3D "disabled"; - }; - - ccu: clock at 01c20000 { - compatible =3D "allwinner,sun8i-h3-ccu"; - reg =3D <0x01c20000 0x400>; - clocks =3D <&osc24M>, <&osc32k>; - clock-names =3D "hosc", "losc"; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - }; - - pio: pinctrl at 01c20800 { - compatible =3D "allwinner,sun8i-h3-pinctrl"; - reg =3D <0x01c20800 0x400>; - interrupts =3D , - ; - clocks =3D <&ccu CLK_BUS_PIO>; - gpio-controller; - #gpio-cells =3D <3>; - interrupt-controller; - #interrupt-cells =3D <3>; - - emac_rgmii_pins: emac0 at 0 { - allwinner,pins =3D "PD0", "PD1", "PD2", "PD3", - "PD4", "PD5", "PD7", - "PD8", "PD9", "PD10", - "PD12", "PD13", "PD15", - "PD16", "PD17"; - allwinner,function =3D "emac"; - allwinner,drive =3D ; - allwinner,pull =3D ; - }; - - mmc0_pins_a: mmc0 at 0 { - allwinner,pins =3D "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - allwinner,function =3D "mmc0"; - allwinner,drive =3D ; - allwinner,pull =3D ; - }; - - mmc0_cd_pin: mmc0_cd_pin at 0 { - allwinner,pins =3D "PF6"; - allwinner,function =3D "gpio_in"; - allwinner,drive =3D ; - allwinner,pull =3D ; - }; - - mmc1_pins_a: mmc1 at 0 { - allwinner,pins =3D "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - allwinner,function =3D "mmc1"; - allwinner,drive =3D ; - allwinner,pull =3D ; - }; - - mmc2_8bit_pins: mmc2_8bit { - allwinner,pins =3D "PC5", "PC6", "PC8", - "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", - "PC15", "PC16"; - allwinner,function =3D "mmc2"; - allwinner,drive =3D ; - allwinner,pull =3D ; - }; - - uart0_pins_a: uart0 at 0 { - allwinner,pins =3D "PA4", "PA5"; - allwinner,function =3D "uart0"; - allwinner,drive =3D ; - allwinner,pull =3D ; - }; - - uart1_pins_a: uart1 at 0 { - allwinner,pins =3D "PG6", "PG7", "PG8", "PG9"; - allwinner,function =3D "uart1"; - allwinner,drive =3D ; - allwinner,pull =3D ; - }; - }; - - timer at 01c20c00 { - compatible =3D "allwinner,sun4i-a10-timer"; - reg =3D <0x01c20c00 0xa0>; - interrupts =3D , - ; - clocks =3D <&osc24M>; - }; - - wdt0: watchdog at 01c20ca0 { - compatible =3D "allwinner,sun6i-a31-wdt"; - reg =3D <0x01c20ca0 0x20>; - interrupts =3D ; - }; - - uart0: serial at 01c28000 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x01c28000 0x400>; - interrupts =3D ; - reg-shift =3D <2>; - reg-io-width =3D <4>; - clocks =3D <&ccu CLK_BUS_UART0>; - resets =3D <&ccu RST_BUS_UART0>; - dmas =3D <&dma 6>, <&dma 6>; - dma-names =3D "rx", "tx"; - status =3D "disabled"; - }; - - uart1: serial at 01c28400 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x01c28400 0x400>; - interrupts =3D ; - reg-shift =3D <2>; - reg-io-width =3D <4>; - clocks =3D <&ccu CLK_BUS_UART1>; - resets =3D <&ccu RST_BUS_UART1>; - dmas =3D <&dma 7>, <&dma 7>; - dma-names =3D "rx", "tx"; - status =3D "disabled"; - }; - - uart2: serial at 01c28800 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x01c28800 0x400>; - interrupts =3D ; - reg-shift =3D <2>; - reg-io-width =3D <4>; - clocks =3D <&ccu CLK_BUS_UART2>; - resets =3D <&ccu RST_BUS_UART2>; - dmas =3D <&dma 8>, <&dma 8>; - dma-names =3D "rx", "tx"; - status =3D "disabled"; - }; - - uart3: serial at 01c28c00 { - compatible =3D "snps,dw-apb-uart"; - reg =3D <0x01c28c00 0x400>; - interrupts =3D ; - reg-shift =3D <2>; - reg-io-width =3D <4>; - clocks =3D <&ccu CLK_BUS_UART3>; - resets =3D <&ccu RST_BUS_UART3>; - dmas =3D <&dma 9>, <&dma 9>; - dma-names =3D "rx", "tx"; - status =3D "disabled"; - }; - - emac: ethernet at 1c30000 { - compatible =3D "allwinner,sun8i-h3-emac"; - reg =3D <0x01c30000 0x104>, <0x01c00030 0x4>; - reg-names =3D "emac", "syscon"; - interrupts =3D ; - resets =3D <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>; - reset-names =3D "ahb", "ephy"; - clocks =3D <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>; - clock-names =3D "ahb", "ephy"; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - - gic: interrupt-controller at 01c81000 { - compatible =3D "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg =3D <0x01c81000 0x1000>, - <0x01c82000 0x1000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells =3D <3>; - interrupts =3D ; - }; - - rtc: rtc at 01f00000 { - compatible =3D "allwinner,sun6i-a31-rtc"; - reg =3D <0x01f00000 0x54>; - interrupts =3D , - ; - }; +&ccu { + compatible =3D "allwinner,sun8i-h3-ccu"; +}; =20 - apb0_reset: reset at 01f014b0 { - reg =3D <0x01f014b0 0x4>; - compatible =3D "allwinner,sun6i-a31-clock-reset"; - #reset-cells =3D <1>; - }; +&mmc0 { + compatible =3D "allwinner,sun7i-a20-mmc"; + clocks =3D <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names =3D "ahb", + "mmc", + "output", + "sample"; +}; =20 - ir: ir at 01f02000 { - compatible =3D "allwinner,sun5i-a13-ir"; - clocks =3D <&apb0_gates 1>, <&ir_clk>; - clock-names =3D "apb", "ir"; - resets =3D <&apb0_reset 1>; - interrupts =3D ; - reg =3D <0x01f02000 0x40>; - status =3D "disabled"; - }; +&mmc1 { + compatible =3D "allwinner,sun7i-a20-mmc"; + clocks =3D <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names =3D "ahb", + "mmc", + "output", + "sample"; +}; =20 - r_pio: pinctrl at 01f02c00 { - compatible =3D "allwinner,sun8i-h3-r-pinctrl"; - reg =3D <0x01f02c00 0x400>; - interrupts =3D ; - clocks =3D <&apb0_gates 0>; - resets =3D <&apb0_reset 0>; - gpio-controller; - #gpio-cells =3D <3>; - interrupt-controller; - #interrupt-cells =3D <3>; +&mmc2 { + compatible =3D "allwinner,sun7i-a20-mmc"; + clocks =3D <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; + clock-names =3D "ahb", + "mmc", + "output", + "sample"; +}; =20 - ir_pins_a: ir at 0 { - allwinner,pins =3D "PL11"; - allwinner,function =3D "s_cir_rx"; - allwinner,drive =3D ; - allwinner,pull =3D ; - }; - }; - }; +&pio { + compatible =3D "allwinner,sun8i-h3-pinctrl"; }; diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi new file mode 100644 index 0000000..1aeeacb --- /dev/null +++ b/arch/arm/dts/sunxi-h3-h5.dtsi @@ -0,0 +1,601 @@ +/* + * Copyright (C) 2015 Jens Kuske + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + clocks { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <24000000>; + clock-output-names =3D "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <32768>; + clock-output-names =3D "osc32k"; + }; + + iosc: internal-osc-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <16000000>; + clock-accuracy =3D <300000000>; + clock-output-names =3D "iosc"; + }; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + dma: dma-controller at 01c02000 { + compatible =3D "allwinner,sun8i-h3-dma"; + reg =3D <0x01c02000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_DMA>; + resets =3D <&ccu RST_BUS_DMA>; + #dma-cells =3D <1>; + }; + + mmc0: mmc at 01c0f000 { + /* compatible and clocks are in per SoC .dtsi file */ + reg =3D <0x01c0f000 0x1000>; + resets =3D <&ccu RST_BUS_MMC0>; + reset-names =3D "ahb"; + interrupts =3D ; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc1: mmc at 01c10000 { + /* compatible and clocks are in per SoC .dtsi file */ + reg =3D <0x01c10000 0x1000>; + resets =3D <&ccu RST_BUS_MMC1>; + reset-names =3D "ahb"; + interrupts =3D ; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc2: mmc at 01c11000 { + /* compatible and clocks are in per SoC .dtsi file */ + reg =3D <0x01c11000 0x1000>; + resets =3D <&ccu RST_BUS_MMC2>; + reset-names =3D "ahb"; + interrupts =3D ; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + usb_otg: usb at 01c19000 { + compatible =3D "allwinner,sun8i-h3-musb"; + reg =3D <0x01c19000 0x400>; + clocks =3D <&ccu CLK_BUS_OTG>; + resets =3D <&ccu RST_BUS_OTG>; + interrupts =3D ; + interrupt-names =3D "mc"; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + extcon =3D <&usbphy 0>; + status =3D "disabled"; + }; + + usbphy: phy at 01c19400 { + compatible =3D "allwinner,sun8i-h3-usb-phy"; + reg =3D <0x01c19400 0x2c>, + <0x01c1a800 0x4>, + <0x01c1b800 0x4>, + <0x01c1c800 0x4>, + <0x01c1d800 0x4>; + reg-names =3D "phy_ctrl", + "pmu0", + "pmu1", + "pmu2", + "pmu3"; + clocks =3D <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>, + <&ccu CLK_USB_PHY3>; + clock-names =3D "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb3_phy"; + resets =3D <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>, + <&ccu RST_USB_PHY3>; + reset-names =3D "usb0_reset", + "usb1_reset", + "usb2_reset", + "usb3_reset"; + status =3D "disabled"; + #phy-cells =3D <1>; + }; + + ehci0: usb at 01c1a000 { + compatible =3D "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg =3D <0x01c1a000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets =3D <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status =3D "disabled"; + }; + + ohci0: usb at 01c1a400 { + compatible =3D "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg =3D <0x01c1a400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets =3D <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status =3D "disabled"; + }; + + ehci1: usb at 01c1b000 { + compatible =3D "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg =3D <0x01c1b000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; + resets =3D <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; + phys =3D <&usbphy 1>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci1: usb at 01c1b400 { + compatible =3D "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg =3D <0x01c1b400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets =3D <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; + phys =3D <&usbphy 1>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ehci2: usb at 01c1c000 { + compatible =3D "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg =3D <0x01c1c000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; + resets =3D <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; + phys =3D <&usbphy 2>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci2: usb at 01c1c400 { + compatible =3D "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg =3D <0x01c1c400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_USB_OHCI2>; + resets =3D <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; + phys =3D <&usbphy 2>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ehci3: usb at 01c1d000 { + compatible =3D "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg =3D <0x01c1d000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; + resets =3D <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; + phys =3D <&usbphy 3>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci3: usb at 01c1d400 { + compatible =3D "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg =3D <0x01c1d400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, + <&ccu CLK_USB_OHCI3>; + resets =3D <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; + phys =3D <&usbphy 3>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ccu: clock at 01c20000 { + /* compatible is in per SoC .dtsi file */ + reg =3D <0x01c20000 0x400>; + clocks =3D <&osc24M>, <&osc32k>; + clock-names =3D "hosc", "losc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + pio: pinctrl at 01c20800 { + /* compatible is in per SoC .dtsi file */ + reg =3D <0x01c20800 0x400>; + interrupts =3D , + ; + clocks =3D <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names =3D "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells =3D <3>; + interrupt-controller; + #interrupt-cells =3D <3>; + + i2c0_pins: i2c0 { + pins =3D "PA11", "PA12"; + function =3D "i2c0"; + }; + + i2c1_pins: i2c1 { + pins =3D "PA18", "PA19"; + function =3D "i2c1"; + }; + + i2c2_pins: i2c2 { + pins =3D "PE12", "PE13"; + function =3D "i2c2"; + }; + + mmc0_pins_a: mmc0 at 0 { + pins =3D "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function =3D "mmc0"; + drive-strength =3D <30>; + bias-pull-up; + }; + + mmc0_cd_pin: mmc0_cd_pin at 0 { + pins =3D "PF6"; + function =3D "gpio_in"; + bias-pull-up; + }; + + mmc1_pins_a: mmc1 at 0 { + pins =3D "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function =3D "mmc1"; + drive-strength =3D <30>; + bias-pull-up; + }; + + mmc2_8bit_pins: mmc2_8bit { + pins =3D "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15", "PC16"; + function =3D "mmc2"; + drive-strength =3D <30>; + bias-pull-up; + }; + + spdif_tx_pins_a: spdif at 0 { + pins =3D "PA17"; + function =3D "spdif"; + }; + + spi0_pins: spi0 { + pins =3D "PC0", "PC1", "PC2", "PC3"; + function =3D "spi0"; + }; + + spi1_pins: spi1 { + pins =3D "PA15", "PA16", "PA14", "PA13"; + function =3D "spi1"; + }; + + uart0_pins_a: uart0 at 0 { + pins =3D "PA4", "PA5"; + function =3D "uart0"; + }; + + uart1_pins: uart1 { + pins =3D "PG6", "PG7"; + function =3D "uart1"; + }; + + uart1_rts_cts_pins: uart1_rts_cts { + pins =3D "PG8", "PG9"; + function =3D "uart1"; + }; + + uart2_pins: uart2 { + pins =3D "PA0", "PA1"; + function =3D "uart2"; + }; + + uart3_pins: uart3 { + pins =3D "PA13", "PA14"; + function =3D "uart3"; + }; + }; + + timer at 01c20c00 { + compatible =3D "allwinner,sun4i-a10-timer"; + reg =3D <0x01c20c00 0xa0>; + interrupts =3D , + ; + clocks =3D <&osc24M>; + }; + + spi0: spi at 01c68000 { + compatible =3D "allwinner,sun8i-h3-spi"; + reg =3D <0x01c68000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names =3D "ahb", "mod"; + dmas =3D <&dma 23>, <&dma 23>; + dma-names =3D "rx", "tx"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi0_pins>; + resets =3D <&ccu RST_BUS_SPI0>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + spi1: spi at 01c69000 { + compatible =3D "allwinner,sun8i-h3-spi"; + reg =3D <0x01c69000 0x1000>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names =3D "ahb", "mod"; + dmas =3D <&dma 24>, <&dma 24>; + dma-names =3D "rx", "tx"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; + resets =3D <&ccu RST_BUS_SPI1>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + wdt0: watchdog at 01c20ca0 { + compatible =3D "allwinner,sun6i-a31-wdt"; + reg =3D <0x01c20ca0 0x20>; + interrupts =3D ; + }; + + spdif: spdif at 01c21000 { + #sound-dai-cells =3D <0>; + compatible =3D "allwinner,sun8i-h3-spdif"; + reg =3D <0x01c21000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; + resets =3D <&ccu RST_BUS_SPDIF>; + clock-names =3D "apb", "spdif"; + dmas =3D <&dma 2>; + dma-names =3D "tx"; + status =3D "disabled"; + }; + + pwm: pwm at 01c21400 { + compatible =3D "allwinner,sun8i-h3-pwm"; + reg =3D <0x01c21400 0x8>; + clocks =3D <&osc24M>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + codec: codec at 01c22c00 { + #sound-dai-cells =3D <0>; + compatible =3D "allwinner,sun8i-h3-codec"; + reg =3D <0x01c22c00 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names =3D "apb", "codec"; + resets =3D <&ccu RST_BUS_CODEC>; + dmas =3D <&dma 15>, <&dma 15>; + dma-names =3D "rx", "tx"; + allwinner,codec-analog-controls =3D <&codec_analog>; + status =3D "disabled"; + }; + + uart0: serial at 01c28000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x01c28000 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART0>; + resets =3D <&ccu RST_BUS_UART0>; + dmas =3D <&dma 6>, <&dma 6>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart1: serial at 01c28400 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x01c28400 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART1>; + resets =3D <&ccu RST_BUS_UART1>; + dmas =3D <&dma 7>, <&dma 7>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart2: serial at 01c28800 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x01c28800 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART2>; + resets =3D <&ccu RST_BUS_UART2>; + dmas =3D <&dma 8>, <&dma 8>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + uart3: serial at 01c28c00 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x01c28c00 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART3>; + resets =3D <&ccu RST_BUS_UART3>; + dmas =3D <&dma 9>, <&dma 9>; + dma-names =3D "rx", "tx"; + status =3D "disabled"; + }; + + i2c0: i2c at 01c2ac00 { + compatible =3D "allwinner,sun6i-a31-i2c"; + reg =3D <0x01c2ac00 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C0>; + resets =3D <&ccu RST_BUS_I2C0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c1: i2c at 01c2b000 { + compatible =3D "allwinner,sun6i-a31-i2c"; + reg =3D <0x01c2b000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C1>; + resets =3D <&ccu RST_BUS_I2C1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c2: i2c at 01c2b400 { + compatible =3D "allwinner,sun6i-a31-i2c"; + reg =3D <0x01c2b000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C2>; + resets =3D <&ccu RST_BUS_I2C2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + gic: interrupt-controller at 01c81000 { + compatible =3D "arm,gic-400"; + reg =3D <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells =3D <3>; + interrupts =3D ; + }; + + rtc: rtc at 01f00000 { + compatible =3D "allwinner,sun6i-a31-rtc"; + reg =3D <0x01f00000 0x54>; + interrupts =3D , + ; + }; + + r_ccu: clock at 1f01400 { + compatible =3D "allwinner,sun50i-a64-r-ccu"; + reg =3D <0x01f01400 0x100>; + clocks =3D <&osc24M>, <&osc32k>, <&iosc>; + clock-names =3D "hosc", "losc", "iosc"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + codec_analog: codec-analog at 01f015c0 { + compatible =3D "allwinner,sun8i-h3-codec-analog"; + reg =3D <0x01f015c0 0x4>; + }; + + ir: ir at 01f02000 { + compatible =3D "allwinner,sun5i-a13-ir"; + clocks =3D <&r_ccu 4>, <&r_ccu 11>; + clock-names =3D "apb", "ir"; + resets =3D <&r_ccu 0>; + interrupts =3D ; + reg =3D <0x01f02000 0x40>; + status =3D "disabled"; + }; + + r_pio: pinctrl at 01f02c00 { + compatible =3D "allwinner,sun8i-h3-r-pinctrl"; + reg =3D <0x01f02c00 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu 3>, <&osc24M>, <&osc32k>; + clock-names =3D "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells =3D <3>; + interrupt-controller; + #interrupt-cells =3D <3>; + + ir_pins_a: ir at 0 { + pins =3D "PL11"; + function =3D "s_cir_rx"; + }; + }; + }; +}; diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig new file mode 100644 index 0000000..74c7d74 --- /dev/null +++ b/configs/nanopi_neo2_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=3Dy +CONFIG_ARCH_SUNXI=3Dy +CONFIG_MACH_SUN50I_H5=3Dy +CONFIG_SPL=3Dy +CONFIG_DRAM_CLK=3D504 +CONFIG_DRAM_ZQ=3D3881977 +CONFIG_DEFAULT_DEVICE_TREE=3D"sun50i-h5-nanopi-neo2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=3Dy +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SUN8I_EMAC=3Dy +CONFIG_USB_EHCI_HCD=3Dy +CONFIG_SPL_SPI_SUNXI=3Dy +CONFIG_SPL_SPI_FLASH_SUPPORT=3Dy diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index a3dbe28..2526f72 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -465,14 +465,20 @@ static int parse_phy_pins(struct udevice *dev) } =20 drive =3D fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, - "allwinner,drive", 4); - pull =3D fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, - "allwinner,pull", 0); + "drive-strength", 40) / 10; + + if (fdt_getprop(gd->fdt_blob, offset, "bias-pull-down", NULL)) + pull =3D 2; + else if (fdt_getprop(gd->fdt_blob, offset, "bias-pull-up", NULL)) + pull =3D 1; + else + pull =3D 0; + for (i =3D 0; ; i++) { int pin; =20 pin_name =3D fdt_stringlist_get(gd->fdt_blob, offset, - "allwinner,pins", i, NULL); + "pins", i, NULL); if (!pin_name) break; if (pin_name[0] !=3D 'P') @@ -488,7 +494,7 @@ static int parse_phy_pins(struct udevice *dev) } =20 if (!i) { - printf("WARNING: emac: cannot find allwinner,pins property\n"); + printf("WARNING: emac: cannot find pins property\n"); return -2; } =20