From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andrew Lunn <andrew@lunn.ch>
Subject: Re: [PATCH v1 1/2] net: emac: fix reset timeout with AR8035 phy
Date: Mon, 5 Jun 2017 23:26:17 +0200
Message-ID: <20170605212617.GC9339@lunn.ch>
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Cc: netdev@vger.kernel.org, "David S . Miller" <davem@davemloft.net>,
        Ivan Mikhaylov <ivan@de.ibm.com>,
        Chris Blake <chrisrblake93@gmail.com>
To: Christian Lamparter <chunkeey@googlemail.com>
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> In order to stay compatible with existing configurations, the
> driver will try the normal reset first and only falls back to
> to the internal clock, after the first reset fails. If the
> second reset fails as well, it will give up as before.

Hi Christian

This gets things probed correctly. But should you swap back to the PHY
clock when the PHY declares the link up? Is there code already to do
this?

	Andrew