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[66.111.4.28]) by mx.google.com with ESMTPS id o199si1438107qke.5.2017.06.13.15.53.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Jun 2017 15:53:53 -0700 (PDT) Received-SPF: pass (google.com: domain of cota@braap.org designates 66.111.4.28 as permitted sender) client-ip=66.111.4.28; Authentication-Results: mx.google.com; dkim=pass header.i=@braap.org; dkim=pass header.i=@messagingengine.com; spf=pass (google.com: domain of cota@braap.org designates 66.111.4.28 as permitted sender) smtp.mailfrom=cota@braap.org Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id B216F20818; Tue, 13 Jun 2017 18:53:52 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Tue, 13 Jun 2017 18:53:52 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=mesmtp; bh=YhiRVYZm0wKYFGPurqFcQYiwhgolOwmoMuhhmJ Cp9rs=; b=mxmEJf7HjWK0uW3IuEY1H3wWfLni/lMD9sO+n1FXpLxUicAVyncKo8 +cO0lICAPdTdOM++O20RcmpJGNco5ha0XjD/XXcNn/RCe09+aVh71WzoOJb0p8qN 8u/rArhLXwGYh4dbZ9JOfIw5O6GGdaAbl6fsW8DLNFUhmsTOV77R8= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=YhiRVYZm0wKYFGPurq FcQYiwhgolOwmoMuhhmJCp9rs=; b=EZW7EpRbVZUslQHLmcZ88tycCHwosiLlcc ORf6OzsQ8WtbCvBtSCk3kQFONZ3eTrHITK8Ym7C/UzfqvtKbuGMB2O2PFmPJsVUt Q44GMfabTHy0xMIwA+zrs++YaJVYr3vp0DSwybVM02QKzVd9OSPGEq+qELMi9Dgp HxBO1T3Sdgx33Kp6jbcpUcTOnLwVEQU5G00tS5Pql8x5dl7g2mFiWR1VW9ue+74Z nVG8kbCwTsiN53ZvKEZYW/EEwjCb7gwtW89RdhOVYv7rj9BwroGdHXEL2PUwo3OQ LY3w3HMcdMXyXcg8wrs+QNIIhCUj8Cjq734+dHCyDaFlf9kab94Q== X-ME-Sender: X-Sasl-enc: JbZO69KACiPiQVXbaADS1wQfzGT0vA8bfWUO9Uq2YvN2 1497394432 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 6CF5E248B0; Tue, 13 Jun 2017 18:53:52 -0400 (EDT) Date: Tue, 13 Jun 2017 18:53:52 -0400 From: "Emilio G. Cota" To: Alex =?iso-8859-1?Q?Benn=E9e?= Cc: Richard Henderson , peter.maydell@linaro.org, pbonzini@redhat.com, edgar.iglesias@xilinx.com, qemu-devel@nongnu.org, Peter Crosthwaite , "open list:ARM" Subject: [PATCH] target/aarch64: exit to main loop after handling MSR Message-ID: <20170613225352.GA26288@flamenco> References: <20170609170100.3599-1-alex.bennee@linaro.org> <20170609170100.3599-4-alex.bennee@linaro.org> <87vao4b4z5.fsf@linaro.org> <9776b437-90b4-f2c2-4a0c-c1c6585379bf@twiddle.net> <20170611050730.GA12317@flamenco> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170611050730.GA12317@flamenco> User-Agent: Mutt/1.5.24 (2015-08-30) X-TUID: zce4QtkBTqGV The appended fixes it for me. Can you please test? [ apply with `git am --scissors' ] Thanks, Emilio ---- 8< ---- Commit e75449a3 ("target/aarch64: optimize indirect branches") causes a regression by which aarch64 guests freeze under TCG with -smp > 1, even with `-accel accel=tcg,thread=single' (i.e. MTTCG disabled). I isolated the problem to the MSR handler. This patch forces an exit after the handler is executed, which fixes the regression. Signed-off-by: Emilio G. Cota --- target/arm/translate-a64.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 860e279..5a609a0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1422,7 +1422,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); tcg_temp_free_i32(tcg_imm); tcg_temp_free_i32(tcg_op); - s->is_jmp = DISAS_UPDATE; + s->is_jmp = DISAS_EXIT; break; } default: @@ -11362,6 +11362,10 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) case DISAS_NEXT: gen_goto_tb(dc, 1, dc->pc); break; + case DISAS_EXIT: + gen_a64_set_pc_im(dc->pc); + tcg_gen_exit_tb(0); + break; default: case DISAS_UPDATE: gen_a64_set_pc_im(dc->pc); -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42003) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKuhG-0001Uu-Dq for qemu-devel@nongnu.org; Tue, 13 Jun 2017 18:54:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKuhF-0006VP-KC for qemu-devel@nongnu.org; Tue, 13 Jun 2017 18:54:02 -0400 Date: Tue, 13 Jun 2017 18:53:52 -0400 From: "Emilio G. Cota" Message-ID: <20170613225352.GA26288@flamenco> References: <20170609170100.3599-1-alex.bennee@linaro.org> <20170609170100.3599-4-alex.bennee@linaro.org> <87vao4b4z5.fsf@linaro.org> <9776b437-90b4-f2c2-4a0c-c1c6585379bf@twiddle.net> <20170611050730.GA12317@flamenco> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170611050730.GA12317@flamenco> Subject: [Qemu-devel] [PATCH] target/aarch64: exit to main loop after handling MSR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex =?iso-8859-1?Q?Benn=E9e?= Cc: Richard Henderson , peter.maydell@linaro.org, pbonzini@redhat.com, edgar.iglesias@xilinx.com, qemu-devel@nongnu.org, Peter Crosthwaite , "open list:ARM" The appended fixes it for me. Can you please test? [ apply with `git am --scissors' ] Thanks, Emilio ---- 8< ---- Commit e75449a3 ("target/aarch64: optimize indirect branches") causes a regression by which aarch64 guests freeze under TCG with -smp > 1, even with `-accel accel=tcg,thread=single' (i.e. MTTCG disabled). I isolated the problem to the MSR handler. This patch forces an exit after the handler is executed, which fixes the regression. Signed-off-by: Emilio G. Cota --- target/arm/translate-a64.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 860e279..5a609a0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1422,7 +1422,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); tcg_temp_free_i32(tcg_imm); tcg_temp_free_i32(tcg_op); - s->is_jmp = DISAS_UPDATE; + s->is_jmp = DISAS_EXIT; break; } default: @@ -11362,6 +11362,10 @@ void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) case DISAS_NEXT: gen_goto_tb(dc, 1, dc->pc); break; + case DISAS_EXIT: + gen_a64_set_pc_im(dc->pc); + tcg_gen_exit_tb(0); + break; default: case DISAS_UPDATE: gen_a64_set_pc_im(dc->pc); -- 2.7.4