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[66.111.4.28]) by mx.google.com with ESMTPS id p68si2048474qkb.237.2017.06.14.22.19.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Jun 2017 22:19:36 -0700 (PDT) Received-SPF: pass (google.com: domain of cota@braap.org designates 66.111.4.28 as permitted sender) client-ip=66.111.4.28; Authentication-Results: mx.google.com; dkim=pass header.i=@braap.org header.b=MsbhmpIO; dkim=pass header.i=@messagingengine.com header.b=pzzNGz1J; spf=pass (google.com: domain of cota@braap.org designates 66.111.4.28 as permitted sender) smtp.mailfrom=cota@braap.org Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id BE34820B8F; Thu, 15 Jun 2017 01:19:35 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Thu, 15 Jun 2017 01:19:35 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-type:date:from:in-reply-to:message-id:mime-version :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=mesmtp; bh=qj+XwvUFtyV/C/sTgK24nS54bRteu9T8ohzCem Vaswg=; b=MsbhmpIObJqdQrpqghN8W7JBXaR/iQVqy52x1PrImQqnojcv3uf/X9 4m6KRRb56oCUSVsp9rje+QcTiRqd3KNa3SXMJGBIfI9GfQuqrq4BK4POtBB6XGVh O3Rr0LEXm6DwUmO0Y+hWjNqKQTp/pwEITt7UvoLbC/hYwUTkF6lw8= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=qj+XwvUFtyV/C/sTgK 24nS54bRteu9T8ohzCemVaswg=; b=pzzNGz1J9v22RLto+sdMdTyMlqHSWu1Y8K npVJPy2R16sPhtq4TCY6tCf430KUKG1ONjkN0N9/yz0GSFlBN+Q6RtYdiyPeP2ts 6JJhJJoHg1bgsnXTCBb/U8Xd9ULAfoslBCwj0lToRnEn0TtlRuweol4mAogVaqgb yXX6epMkygjECCD6dfBp+VM+Cjl5nVymI80QWfI11STzPswzWkwDvmCZEM6eG3xX UNUVQwu1EBTu/rDb+3dUrGIT1jHFpqph9MNg4CRDyR/Ecc2dt5YXIMtY8QlhLlpg l6tCiq81hf4jx8pkWcfSEide3TZyjoh3K63J4CPqArD/fG/16U2w== X-ME-Sender: X-Sasl-enc: 4XinnDWL2/i2fJMVfRHHUJafsIg1iBY6AHgzHdACQzkE 1497503975 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 7583624767; Thu, 15 Jun 2017 01:19:35 -0400 (EDT) Date: Thu, 15 Jun 2017 01:19:35 -0400 From: "Emilio G. Cota" To: Richard Henderson Cc: qemu-devel@nongnu.org, alex.bennee@linaro.org, pbonzini@redhat.com, qemu-arm@nongnu.org, Peter Maydell Subject: Re: [PATCH] target/aarch64: exit to main loop after 'msr daifclr' Message-ID: <20170615051935.GA6079@flamenco> References: <20170614194821.8754-1-rth@twiddle.net> <20170614194821.8754-6-rth@twiddle.net> <20170614203343.GB8420@flamenco> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) X-TUID: dY6DOzfdEOZ+ On Wed, Jun 14, 2017 at 18:20:29 -0700, Richard Henderson wrote: > On 06/14/2017 01:33 PM, Emilio G. Cota wrote: > >On Wed, Jun 14, 2017 at 12:48:21 -0700, Richard Henderson wrote: > >>Exit to cpu loop so we reevaluate cpu_arm_hw_interrupts. > >> > >>Cc: qemu-arm@nongnu.org > >>Cc: Peter Maydell > >>Signed-off-by: Richard Henderson > >>--- > >> target/arm/translate-a64.c | 7 ++++++- > >> 1 file changed, 6 insertions(+), 1 deletion(-) > >> > >>diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > >>index 860e279..e55547d 100644 > >>--- a/target/arm/translate-a64.c > >>+++ b/target/arm/translate-a64.c > >>@@ -1422,7 +1422,9 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, > >> gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); > >> tcg_temp_free_i32(tcg_imm); > >> tcg_temp_free_i32(tcg_op); > >>- s->is_jmp = DISAS_UPDATE; > >>+ /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ > >>+ gen_a64_set_pc_im(s->pc); > > > >For op != 0x1f we end up setting the pc twice (first here, then in > >the switch statement). It's still correct though. > > No, that's why I switched to DISAS_JUMP. > (snip) > >+ case DISAS_EXIT: > >+ gen_a64_set_pc_im(dc->pc); > >+ tcg_gen_exit_tb(0); > >+ break; > > This gives translate-a64.c and translate.c different semantics for > DISAS_EXIT. I considered that to be a bad thing. Agreed with the above two. Sorry I missed this in my first read of the patch, it seems that my writing of my version of this patch impaired my ability to review another version :-) Thanks for the clarifications! Reviewed-by: Emilio G. Cota Tested-by: Emilio G. Cota E. From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60029) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dLNC5-0001Cv-3R for qemu-devel@nongnu.org; Thu, 15 Jun 2017 01:19:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dLNC4-0000xW-5H for qemu-devel@nongnu.org; Thu, 15 Jun 2017 01:19:45 -0400 Date: Thu, 15 Jun 2017 01:19:35 -0400 From: "Emilio G. Cota" Message-ID: <20170615051935.GA6079@flamenco> References: <20170614194821.8754-1-rth@twiddle.net> <20170614194821.8754-6-rth@twiddle.net> <20170614203343.GB8420@flamenco> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH] target/aarch64: exit to main loop after 'msr daifclr' List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, alex.bennee@linaro.org, pbonzini@redhat.com, qemu-arm@nongnu.org, Peter Maydell On Wed, Jun 14, 2017 at 18:20:29 -0700, Richard Henderson wrote: > On 06/14/2017 01:33 PM, Emilio G. Cota wrote: > >On Wed, Jun 14, 2017 at 12:48:21 -0700, Richard Henderson wrote: > >>Exit to cpu loop so we reevaluate cpu_arm_hw_interrupts. > >> > >>Cc: qemu-arm@nongnu.org > >>Cc: Peter Maydell > >>Signed-off-by: Richard Henderson > >>--- > >> target/arm/translate-a64.c | 7 ++++++- > >> 1 file changed, 6 insertions(+), 1 deletion(-) > >> > >>diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > >>index 860e279..e55547d 100644 > >>--- a/target/arm/translate-a64.c > >>+++ b/target/arm/translate-a64.c > >>@@ -1422,7 +1422,9 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, > >> gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); > >> tcg_temp_free_i32(tcg_imm); > >> tcg_temp_free_i32(tcg_op); > >>- s->is_jmp = DISAS_UPDATE; > >>+ /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ > >>+ gen_a64_set_pc_im(s->pc); > > > >For op != 0x1f we end up setting the pc twice (first here, then in > >the switch statement). It's still correct though. > > No, that's why I switched to DISAS_JUMP. > (snip) > >+ case DISAS_EXIT: > >+ gen_a64_set_pc_im(dc->pc); > >+ tcg_gen_exit_tb(0); > >+ break; > > This gives translate-a64.c and translate.c different semantics for > DISAS_EXIT. I considered that to be a bad thing. Agreed with the above two. Sorry I missed this in my first read of the patch, it seems that my writing of my version of this patch impaired my ability to review another version :-) Thanks for the clarifications! Reviewed-by: Emilio G. Cota Tested-by: Emilio G. Cota E.