From: "Michael S. Tsirkin" <mst@redhat.com>
To: Ladi Prosek <lprosek@redhat.com>
Cc: qemu-devel@nongnu.org, peterx@redhat.com
Subject: Re: [Qemu-devel] [PATCH] intel_iommu: relax iq tail check on VTD_GCMD_QIE enable
Date: Fri, 16 Jun 2017 17:41:14 +0300 [thread overview]
Message-ID: <20170616174036-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <20170616114443.25838-1-lprosek@redhat.com>
On Fri, Jun 16, 2017 at 01:44:43PM +0200, Ladi Prosek wrote:
> The VT-d spec (section 6.5.2) prescribes software to zero the
> Invalidation Queue Tail Register before enabling the VTD_GCMD_QIE
> Global Command Register bit. Windows Server 2012 R2 and possibly
> other older Windows versions violate the protocol and set a
> non-zero queue tail first, which in effect makes them crash early
> on boot with -device intel-iommu,intremap=on.
>
> This commit relaxes the check and instead of failing to enable
> VTD_GCMD_QIE with "error: can't enable Queued Invalidation", it
> behaves as if the tail register was set just after enabling
> VTD_GCMD_QIE (see vtd_handle_iqt_write).
>
> Signed-off-by: Ladi Prosek <lprosek@redhat.com>
Thanks!
This conflicts with Peter's tracing which I merged -
could you rework on top of that pls?
the new warning should be a trace point too I imagine.
> ---
> hw/i386/intel_iommu.c | 32 +++++++++++++++-----------------
> 1 file changed, 15 insertions(+), 17 deletions(-)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 15610b9..f2cb822 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -1466,10 +1466,7 @@ static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val)
> return iaig;
> }
>
> -static inline bool vtd_queued_inv_enable_check(IntelIOMMUState *s)
> -{
> - return s->iq_tail == 0;
> -}
> +static void vtd_fetch_inv_desc(IntelIOMMUState *s);
>
> static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s)
> {
> @@ -1483,19 +1480,20 @@ static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en)
>
> VTD_DPRINTF(INV, "Queued Invalidation Enable %s", (en ? "on" : "off"));
> if (en) {
> - if (vtd_queued_inv_enable_check(s)) {
> - s->iq = iqa_val & VTD_IQA_IQA_MASK;
> - /* 2^(x+8) entries */
> - s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8);
> - s->qi_enabled = true;
> - VTD_DPRINTF(INV, "DMAR_IQA_REG 0x%"PRIx64, iqa_val);
> - VTD_DPRINTF(INV, "Invalidation Queue addr 0x%"PRIx64 " size %d",
> - s->iq, s->iq_size);
> - /* Ok - report back to driver */
> - vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES);
> - } else {
> - VTD_DPRINTF(GENERAL, "error: can't enable Queued Invalidation: "
> - "tail %"PRIu16, s->iq_tail);
> + s->iq = iqa_val & VTD_IQA_IQA_MASK;
> + /* 2^(x+8) entries */
> + s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8);
> + s->qi_enabled = true;
> + VTD_DPRINTF(INV, "DMAR_IQA_REG 0x%"PRIx64, iqa_val);
> + VTD_DPRINTF(INV, "Invalidation Queue addr 0x%"PRIx64 " size %d",
> + s->iq, s->iq_size);
> + /* Ok - report back to driver */
> + vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES);
> +
> + if (s->iq_tail != 0 &&
> + !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
> + VTD_DPRINTF(INV, "warning: QI enabled with non-zero tail");
> + vtd_fetch_inv_desc(s);
> }
> } else {
> if (vtd_queued_inv_disable_check(s)) {
> --
> 2.9.3
next prev parent reply other threads:[~2017-06-16 14:41 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-16 11:44 [Qemu-devel] [PATCH] intel_iommu: relax iq tail check on VTD_GCMD_QIE enable Ladi Prosek
2017-06-16 14:41 ` Michael S. Tsirkin [this message]
2017-06-19 6:42 ` Peter Xu
2017-06-19 7:33 ` Ladi Prosek
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