diff for duplicates of <20170620180618.GE28035@arm.com> diff --git a/a/1.txt b/N1/1.txt index 4c7e2ab..f5f3175 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,5 +1,5 @@ On Tue, Jun 20, 2017 at 07:47:38PM +0530, Geetha sowjanya wrote: -> From: Linu Cherian <linu.cherian(a)cavium.com> +> From: Linu Cherian <linu.cherian@cavium.com> > > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space > and PAGE0_REGS_ONLY option is enabled as an errata workaround. @@ -11,8 +11,8 @@ On Tue, Jun 20, 2017 at 07:47:38PM +0530, Geetha sowjanya wrote: > For this, arm_smmu_device_dt_probe/acpi_probe has been moved before > platform_get_resource call, so that SMMU options are set beforehand. > -> Signed-off-by: Linu Cherian <linu.cherian(a)cavium.com> -> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula(a)cavium.com> +> Signed-off-by: Linu Cherian <linu.cherian@cavium.com> +> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@cavium.com> > --- > Documentation/arm64/silicon-errata.txt | 1 + > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 ++ diff --git a/a/content_digest b/N1/content_digest index f6b5ed9..67e243f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,11 +1,34 @@ - "From\0Will Deacon <will.deacon at arm.com>\0" - "Subject\0Re: [Devel] [PATCH v8 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74\0" + "ref\01497968259-16390-1-git-send-email-gakula@caviumnetworks.com\0" + "ref\01497968259-16390-3-git-send-email-gakula@caviumnetworks.com\0" + "From\0Will Deacon <will.deacon@arm.com>\0" + "Subject\0Re: [PATCH v8 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74\0" "Date\0Tue, 20 Jun 2017 19:06:19 +0100\0" - "To\0devel@acpica.org\0" - "\01:1\0" + "To\0Geetha sowjanya <gakula@caviumnetworks.com>\0" + "Cc\0robin.murphy@arm.com" + lorenzo.pieralisi@arm.com + hanjun.guo@linaro.org + sudeep.holla@arm.com + iommu@lists.linux-foundation.org + robert.moore@intel.com + lv.zheng@intel.com + rjw@rjwysocki.net + jcm@redhat.com + linux-kernel@vger.kernel.org + robert.richter@cavium.com + catalin.marinas@arm.com + sgoutham@cavium.com + linux-arm-kernel@lists.infradead.org + linux-acpi@vger.kernel.org + geethasowjanya.akula@gmail.com + devel@acpica.org + linu.cherian@cavium.com + Charles.Garcia-Tobin@arm.com + robh@kernel.org + " Geetha Sowjanya <geethasowjanya.akula@cavium.com>\0" + "\00:1\0" "b\0" "On Tue, Jun 20, 2017 at 07:47:38PM +0530, Geetha sowjanya wrote:\n" - "> From: Linu Cherian <linu.cherian(a)cavium.com>\n" + "> From: Linu Cherian <linu.cherian@cavium.com>\n" "> \n" "> Cavium ThunderX2 SMMU implementation doesn't support page 1 register space\n" "> and PAGE0_REGS_ONLY option is enabled as an errata workaround.\n" @@ -17,8 +40,8 @@ "> For this, arm_smmu_device_dt_probe/acpi_probe has been moved before\n" "> platform_get_resource call, so that SMMU options are set beforehand.\n" "> \n" - "> Signed-off-by: Linu Cherian <linu.cherian(a)cavium.com>\n" - "> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula(a)cavium.com>\n" + "> Signed-off-by: Linu Cherian <linu.cherian@cavium.com>\n" + "> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@cavium.com>\n" "> ---\n" "> Documentation/arm64/silicon-errata.txt | 1 +\n" "> .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 ++\n" @@ -54,4 +77,4 @@ "\n" Will -fd3c5f97fcfa15d418a3df9d636986a909426ed3cc95c1e685dd2b2a60d758cc +e1f63544c8ced72543716f3a5eca98394fa51385e0494d2d82e05301bcd913db
diff --git a/a/1.txt b/N2/1.txt index 4c7e2ab..f5f3175 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,5 +1,5 @@ On Tue, Jun 20, 2017 at 07:47:38PM +0530, Geetha sowjanya wrote: -> From: Linu Cherian <linu.cherian(a)cavium.com> +> From: Linu Cherian <linu.cherian@cavium.com> > > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space > and PAGE0_REGS_ONLY option is enabled as an errata workaround. @@ -11,8 +11,8 @@ On Tue, Jun 20, 2017 at 07:47:38PM +0530, Geetha sowjanya wrote: > For this, arm_smmu_device_dt_probe/acpi_probe has been moved before > platform_get_resource call, so that SMMU options are set beforehand. > -> Signed-off-by: Linu Cherian <linu.cherian(a)cavium.com> -> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula(a)cavium.com> +> Signed-off-by: Linu Cherian <linu.cherian@cavium.com> +> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@cavium.com> > --- > Documentation/arm64/silicon-errata.txt | 1 + > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 ++ diff --git a/a/content_digest b/N2/content_digest index f6b5ed9..51eeb9e 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,11 +1,13 @@ - "From\0Will Deacon <will.deacon at arm.com>\0" - "Subject\0Re: [Devel] [PATCH v8 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74\0" + "ref\01497968259-16390-1-git-send-email-gakula@caviumnetworks.com\0" + "ref\01497968259-16390-3-git-send-email-gakula@caviumnetworks.com\0" + "From\0will.deacon@arm.com (Will Deacon)\0" + "Subject\0[PATCH v8 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74\0" "Date\0Tue, 20 Jun 2017 19:06:19 +0100\0" - "To\0devel@acpica.org\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "On Tue, Jun 20, 2017 at 07:47:38PM +0530, Geetha sowjanya wrote:\n" - "> From: Linu Cherian <linu.cherian(a)cavium.com>\n" + "> From: Linu Cherian <linu.cherian@cavium.com>\n" "> \n" "> Cavium ThunderX2 SMMU implementation doesn't support page 1 register space\n" "> and PAGE0_REGS_ONLY option is enabled as an errata workaround.\n" @@ -17,8 +19,8 @@ "> For this, arm_smmu_device_dt_probe/acpi_probe has been moved before\n" "> platform_get_resource call, so that SMMU options are set beforehand.\n" "> \n" - "> Signed-off-by: Linu Cherian <linu.cherian(a)cavium.com>\n" - "> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula(a)cavium.com>\n" + "> Signed-off-by: Linu Cherian <linu.cherian@cavium.com>\n" + "> Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@cavium.com>\n" "> ---\n" "> Documentation/arm64/silicon-errata.txt | 1 +\n" "> .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 ++\n" @@ -54,4 +56,4 @@ "\n" Will -fd3c5f97fcfa15d418a3df9d636986a909426ed3cc95c1e685dd2b2a60d758cc +16eb9b0b5f42c3876d014dcce3e561466dcb0954006914734ab5ac6f3997b928
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