From: Vinod Koul <vinod.koul@intel.com>
To: Thomas Breitung <thomas.breitung@izt-labs.de>
Cc: linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, Li Yang <leoli@freescale.com>,
Zhang Wei <zw@zh-kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
Wolfgang Ocker <weo@reccoware.de>
Subject: Re: [PATCH] dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly
Date: Thu, 22 Jun 2017 18:31:57 +0530 [thread overview]
Message-ID: <20170622130157.GU19154@localhost> (raw)
In-Reply-To: <20170619144004.18224-1-thomas.breitung@izt-labs.de>
On Mon, Jun 19, 2017 at 04:40:04PM +0200, Thomas Breitung wrote:
> The bits of BWC, DAHTS and SAHTS in the DMA mode register must be cleared
> before a new value can be or-ed in.
Applied, thanks
--
~Vinod
prev parent reply other threads:[~2017-06-22 12:59 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-19 14:40 [PATCH] dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly Thomas Breitung
2017-06-22 13:01 ` Vinod Koul [this message]
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