diff for duplicates of <20170622182226.GH15336@arm.com> diff --git a/a/1.txt b/N1/1.txt index 170be74..ff2037e 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,7 +1,7 @@ Hi Geetha, On Thu, Jun 22, 2017 at 05:35:38PM +0530, Geetha sowjanya wrote: -> From: Geetha Sowjanya <geethasowjanya.akula(a)cavium.com> +> From: Geetha Sowjanya <geethasowjanya.akula@cavium.com> > > Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq > lines for gerror, eventq and cmdq-sync. @@ -9,7 +9,7 @@ On Thu, Jun 22, 2017 at 05:35:38PM +0530, Geetha sowjanya wrote: > New named irq "combined" is set as a errata workaround, which allows to > share the irq line by register single irq handler for all the interrupts. > -> Signed-off-by: Geetha sowjanya <gakula(a)caviumnetworks.com> +> Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com> > --- > Documentation/arm64/silicon-errata.txt | 1 + > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 1 + diff --git a/a/content_digest b/N1/content_digest index 7e6f387..b73dc68 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,13 +1,36 @@ - "From\0Will Deacon <will.deacon at arm.com>\0" - "Subject\0Re: [Devel] [PATCH v9 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126\0" + "ref\01498133138-20244-1-git-send-email-gakula@caviumnetworks.com\0" + "ref\01498133138-20244-4-git-send-email-gakula@caviumnetworks.com\0" + "From\0Will Deacon <will.deacon@arm.com>\0" + "Subject\0Re: [PATCH v9 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126\0" "Date\0Thu, 22 Jun 2017 19:22:26 +0100\0" - "To\0devel@acpica.org\0" - "\01:1\0" + "To\0Geetha sowjanya <gakula@caviumnetworks.com>\0" + "Cc\0robin.murphy@arm.com" + lorenzo.pieralisi@arm.com + hanjun.guo@linaro.org + sudeep.holla@arm.com + iommu@lists.linux-foundation.org + robert.moore@intel.com + lv.zheng@intel.com + rjw@rjwysocki.net + jcm@redhat.com + linux-kernel@vger.kernel.org + robert.richter@cavium.com + catalin.marinas@arm.com + sgoutham@cavium.com + linux-arm-kernel@lists.infradead.org + linux-acpi@vger.kernel.org + geethasowjanya.akula@gmail.com + devel@acpica.org + linu.cherian@cavium.com + Charles.Garcia-Tobin@arm.com + robh@kernel.org + " Geetha Sowjanya <geethasowjanya.akula@cavium.com>\0" + "\00:1\0" "b\0" "Hi Geetha,\n" "\n" "On Thu, Jun 22, 2017 at 05:35:38PM +0530, Geetha sowjanya wrote:\n" - "> From: Geetha Sowjanya <geethasowjanya.akula(a)cavium.com>\n" + "> From: Geetha Sowjanya <geethasowjanya.akula@cavium.com>\n" "> \n" "> Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq\n" "> lines for gerror, eventq and cmdq-sync.\n" @@ -15,7 +38,7 @@ "> New named irq \"combined\" is set as a errata workaround, which allows to\n" "> share the irq line by register single irq handler for all the interrupts.\n" "> \n" - "> Signed-off-by: Geetha sowjanya <gakula(a)caviumnetworks.com>\n" + "> Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com>\n" "> ---\n" "> Documentation/arm64/silicon-errata.txt | 1 +\n" "> .../devicetree/bindings/iommu/arm,smmu-v3.txt | 1 +\n" @@ -175,4 +198,4 @@ "\n" Will -a09971ef84f99d69292643f9e31ab040c2c97c23dd3f585f7d81ffd993058bf4 +b61e8d8ab402d8dcf0e8d6591d8be6506de1e49eeb1746913447c384c3cd4341
diff --git a/a/1.txt b/N2/1.txt index 170be74..ff2037e 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,7 +1,7 @@ Hi Geetha, On Thu, Jun 22, 2017 at 05:35:38PM +0530, Geetha sowjanya wrote: -> From: Geetha Sowjanya <geethasowjanya.akula(a)cavium.com> +> From: Geetha Sowjanya <geethasowjanya.akula@cavium.com> > > Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq > lines for gerror, eventq and cmdq-sync. @@ -9,7 +9,7 @@ On Thu, Jun 22, 2017 at 05:35:38PM +0530, Geetha sowjanya wrote: > New named irq "combined" is set as a errata workaround, which allows to > share the irq line by register single irq handler for all the interrupts. > -> Signed-off-by: Geetha sowjanya <gakula(a)caviumnetworks.com> +> Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com> > --- > Documentation/arm64/silicon-errata.txt | 1 + > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 1 + diff --git a/a/content_digest b/N2/content_digest index 7e6f387..dc0de43 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,13 +1,15 @@ - "From\0Will Deacon <will.deacon at arm.com>\0" - "Subject\0Re: [Devel] [PATCH v9 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126\0" + "ref\01498133138-20244-1-git-send-email-gakula@caviumnetworks.com\0" + "ref\01498133138-20244-4-git-send-email-gakula@caviumnetworks.com\0" + "From\0will.deacon@arm.com (Will Deacon)\0" + "Subject\0[PATCH v9 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126\0" "Date\0Thu, 22 Jun 2017 19:22:26 +0100\0" - "To\0devel@acpica.org\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "Hi Geetha,\n" "\n" "On Thu, Jun 22, 2017 at 05:35:38PM +0530, Geetha sowjanya wrote:\n" - "> From: Geetha Sowjanya <geethasowjanya.akula(a)cavium.com>\n" + "> From: Geetha Sowjanya <geethasowjanya.akula@cavium.com>\n" "> \n" "> Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq\n" "> lines for gerror, eventq and cmdq-sync.\n" @@ -15,7 +17,7 @@ "> New named irq \"combined\" is set as a errata workaround, which allows to\n" "> share the irq line by register single irq handler for all the interrupts.\n" "> \n" - "> Signed-off-by: Geetha sowjanya <gakula(a)caviumnetworks.com>\n" + "> Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com>\n" "> ---\n" "> Documentation/arm64/silicon-errata.txt | 1 +\n" "> .../devicetree/bindings/iommu/arm,smmu-v3.txt | 1 +\n" @@ -175,4 +177,4 @@ "\n" Will -a09971ef84f99d69292643f9e31ab040c2c97c23dd3f585f7d81ffd993058bf4 +96fe26d21a5978dba33eb8ab4e574aa379c43155d030cd27b17d9b88f6747381
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