From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: multipart/mixed; boundary="===============7911050555986565155==" MIME-Version: 1.0 From: Will Deacon Subject: Re: [Devel] [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds Date: Thu, 22 Jun 2017 19:22:57 +0100 Message-ID: <20170622182257.GI15336@arm.com> In-Reply-To: 1498133138-20244-1-git-send-email-gakula@caviumnetworks.com List-ID: To: devel@acpica.org --===============7911050555986565155== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable On Thu, Jun 22, 2017 at 05:35:35PM +0530, Geetha sowjanya wrote: > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 > SMMU register alias Page 1 is not implemented > 2. Errata ID #126 > SMMU doesnt support unique IRQ lines and also MSI for gerror, > eventq and cmdq-sync > = > The following patchset does software workaround for these two erratas. I've picked up the first two patches, and left comments on the final patch. Will --===============7911050555986565155==-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds Date: Thu, 22 Jun 2017 19:22:57 +0100 Message-ID: <20170622182257.GI15336@arm.com> References: <1498133138-20244-1-git-send-email-gakula@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1498133138-20244-1-git-send-email-gakula-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Geetha sowjanya Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, devel-E0kO6a4B6psdnm+yROfE0A@public.gmane.org, catalin.marinas-5wv7dgnIgG8@public.gmane.org, Charles.Garcia-Tobin-5wv7dgnIgG8@public.gmane.org, geethasowjanya.akula-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, jcm-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, linu.cherian-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org, rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org, robert.moore-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, sudeep.holla-5wv7dgnIgG8@public.gmane.org, sgoutham-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org, robert.richter-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org, lv.zheng-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org List-Id: linux-acpi@vger.kernel.org On Thu, Jun 22, 2017 at 05:35:35PM +0530, Geetha sowjanya wrote: > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 > SMMU register alias Page 1 is not implemented > 2. Errata ID #126 > SMMU doesnt support unique IRQ lines and also MSI for gerror, > eventq and cmdq-sync > > The following patchset does software workaround for these two erratas. I've picked up the first two patches, and left comments on the final patch. Will From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Thu, 22 Jun 2017 19:22:57 +0100 Subject: [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds In-Reply-To: <1498133138-20244-1-git-send-email-gakula@caviumnetworks.com> References: <1498133138-20244-1-git-send-email-gakula@caviumnetworks.com> Message-ID: <20170622182257.GI15336@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Jun 22, 2017 at 05:35:35PM +0530, Geetha sowjanya wrote: > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 > SMMU register alias Page 1 is not implemented > 2. Errata ID #126 > SMMU doesnt support unique IRQ lines and also MSI for gerror, > eventq and cmdq-sync > > The following patchset does software workaround for these two erratas. I've picked up the first two patches, and left comments on the final patch. Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753586AbdFVSWr (ORCPT ); Thu, 22 Jun 2017 14:22:47 -0400 Received: from foss.arm.com ([217.140.101.70]:42658 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751221AbdFVSWp (ORCPT ); Thu, 22 Jun 2017 14:22:45 -0400 Date: Thu, 22 Jun 2017 19:22:57 +0100 From: Will Deacon To: Geetha sowjanya Cc: robin.murphy@arm.com, lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org, sudeep.holla@arm.com, iommu@lists.linux-foundation.org, robert.moore@intel.com, lv.zheng@intel.com, rjw@rjwysocki.net, jcm@redhat.com, linux-kernel@vger.kernel.org, robert.richter@cavium.com, catalin.marinas@arm.com, sgoutham@cavium.com, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, geethasowjanya.akula@gmail.com, devel@acpica.org, linu.cherian@cavium.com, Charles.Garcia-Tobin@arm.com, robh@kernel.org Subject: Re: [PATCH v9 0/3] Cavium ThunderX2 SMMUv3 errata workarounds Message-ID: <20170622182257.GI15336@arm.com> References: <1498133138-20244-1-git-send-email-gakula@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1498133138-20244-1-git-send-email-gakula@caviumnetworks.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jun 22, 2017 at 05:35:35PM +0530, Geetha sowjanya wrote: > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 > SMMU register alias Page 1 is not implemented > 2. Errata ID #126 > SMMU doesnt support unique IRQ lines and also MSI for gerror, > eventq and cmdq-sync > > The following patchset does software workaround for these two erratas. I've picked up the first two patches, and left comments on the final patch. Will