diff for duplicates of <20170627140559.GK14041@arm.com> diff --git a/a/1.txt b/N1/1.txt index 0f1c8a5..7abc9d7 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ On Tue, Jun 27, 2017 at 03:56:10PM +0200, Robert Richter wrote: > On 23.06.17 19:04:36, Geetha sowjanya wrote: -> > From: Geetha Sowjanya <geethasowjanya.akula(a)cavium.com> +> > From: Geetha Sowjanya <geethasowjanya.akula@cavium.com> > > > > Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq > > lines for gerror, eventq and cmdq-sync. @@ -8,7 +8,7 @@ On Tue, Jun 27, 2017 at 03:56:10PM +0200, Robert Richter wrote: > > New named irq "combined" is set as a errata workaround, which allows to > > share the irq line by register single irq handler for all the interrupts. > > -> > Signed-off-by: Geetha sowjanya <gakula(a)caviumnetworks.com> +> > Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com> > > --- > > Documentation/arm64/silicon-errata.txt | 1 + > > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 + diff --git a/a/content_digest b/N1/content_digest index bcf0ef4..81d1946 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,12 +1,33 @@ - "From\0Will Deacon <will.deacon at arm.com>\0" + "ref\01498224876-5200-1-git-send-email-gakula@caviumnetworks.com\0" + "ref\020170627135610.GX658@rric.localdomain\0" + "From\0Will Deacon <will.deacon@arm.com>\0" "Subject\0Re: [Devel] [RESEND PATCH v9 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126\0" "Date\0Tue, 27 Jun 2017 15:06:00 +0100\0" - "To\0devel@acpica.org\0" - "\01:1\0" + "To\0Robert Richter <robert.richter@cavium.com>\0" + "Cc\0Geetha sowjanya <gakula@caviumnetworks.com>" + robin.murphy@arm.com + lorenzo.pieralisi@arm.com + hanjun.guo@linaro.org + sudeep.holla@arm.com + iommu@lists.linux-foundation.org + robh@kernel.org + Charles.Garcia-Tobin@arm.com + Geetha Sowjanya <geethasowjanya.akula@cavium.com> + geethasowjanya.akula@gmail.com + jcm@redhat.com + linu.cherian@cavium.com + rjw@rjwysocki.net + linux-kernel@vger.kernel.org + linux-acpi@vger.kernel.org + catalin.marinas@arm.com + sgoutham@cavium.com + linux-arm-kernel@lists.infradead.org + " devel@acpica.org\0" + "\00:1\0" "b\0" "On Tue, Jun 27, 2017 at 03:56:10PM +0200, Robert Richter wrote:\n" "> On 23.06.17 19:04:36, Geetha sowjanya wrote:\n" - "> > From: Geetha Sowjanya <geethasowjanya.akula(a)cavium.com>\n" + "> > From: Geetha Sowjanya <geethasowjanya.akula@cavium.com>\n" "> > \n" "> > Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq\n" "> > lines for gerror, eventq and cmdq-sync.\n" @@ -14,7 +35,7 @@ "> > New named irq \"combined\" is set as a errata workaround, which allows to\n" "> > share the irq line by register single irq handler for all the interrupts.\n" "> > \n" - "> > Signed-off-by: Geetha sowjanya <gakula(a)caviumnetworks.com>\n" + "> > Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com>\n" "> > ---\n" "> > Documentation/arm64/silicon-errata.txt | 1 +\n" "> > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 +\n" @@ -60,4 +81,4 @@ "\n" Will -f6e1251ad620bdeb08d5eb8bd33a5de984f7c35bd5a523358c3b676452e25dd6 +2183bb30aed837ecafbca65fa35a120cb34bf0bff23a2060888847d9efe3074d
diff --git a/a/1.txt b/N2/1.txt index 0f1c8a5..7abc9d7 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,6 +1,6 @@ On Tue, Jun 27, 2017 at 03:56:10PM +0200, Robert Richter wrote: > On 23.06.17 19:04:36, Geetha sowjanya wrote: -> > From: Geetha Sowjanya <geethasowjanya.akula(a)cavium.com> +> > From: Geetha Sowjanya <geethasowjanya.akula@cavium.com> > > > > Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq > > lines for gerror, eventq and cmdq-sync. @@ -8,7 +8,7 @@ On Tue, Jun 27, 2017 at 03:56:10PM +0200, Robert Richter wrote: > > New named irq "combined" is set as a errata workaround, which allows to > > share the irq line by register single irq handler for all the interrupts. > > -> > Signed-off-by: Geetha sowjanya <gakula(a)caviumnetworks.com> +> > Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com> > > --- > > Documentation/arm64/silicon-errata.txt | 1 + > > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 + diff --git a/a/content_digest b/N2/content_digest index bcf0ef4..daa099d 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,12 +1,14 @@ - "From\0Will Deacon <will.deacon at arm.com>\0" - "Subject\0Re: [Devel] [RESEND PATCH v9 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126\0" + "ref\01498224876-5200-1-git-send-email-gakula@caviumnetworks.com\0" + "ref\020170627135610.GX658@rric.localdomain\0" + "From\0will.deacon@arm.com (Will Deacon)\0" + "Subject\0[Devel] [RESEND PATCH v9 3/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126\0" "Date\0Tue, 27 Jun 2017 15:06:00 +0100\0" - "To\0devel@acpica.org\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "On Tue, Jun 27, 2017 at 03:56:10PM +0200, Robert Richter wrote:\n" "> On 23.06.17 19:04:36, Geetha sowjanya wrote:\n" - "> > From: Geetha Sowjanya <geethasowjanya.akula(a)cavium.com>\n" + "> > From: Geetha Sowjanya <geethasowjanya.akula@cavium.com>\n" "> > \n" "> > Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq\n" "> > lines for gerror, eventq and cmdq-sync.\n" @@ -14,7 +16,7 @@ "> > New named irq \"combined\" is set as a errata workaround, which allows to\n" "> > share the irq line by register single irq handler for all the interrupts.\n" "> > \n" - "> > Signed-off-by: Geetha sowjanya <gakula(a)caviumnetworks.com>\n" + "> > Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com>\n" "> > ---\n" "> > Documentation/arm64/silicon-errata.txt | 1 +\n" "> > .../devicetree/bindings/iommu/arm,smmu-v3.txt | 6 +\n" @@ -60,4 +62,4 @@ "\n" Will -f6e1251ad620bdeb08d5eb8bd33a5de984f7c35bd5a523358c3b676452e25dd6 +4c657acab5d94c72b3739121adb8d747f80c6f613fbf081ff32dca320c5aaebf
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