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[66.111.4.29]) by mx.google.com with ESMTPS id q55si6078891qtf.382.2017.06.29.15.52.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Jun 2017 15:52:26 -0700 (PDT) Received-SPF: pass (google.com: domain of cota@braap.org designates 66.111.4.29 as permitted sender) client-ip=66.111.4.29; Authentication-Results: mx.google.com; dkim=pass header.i=@braap.org header.b=j+UedUsK; dkim=pass header.i=@messagingengine.com header.b=Gh2vFSoU; spf=pass (google.com: domain of cota@braap.org designates 66.111.4.29 as permitted sender) smtp.mailfrom=cota@braap.org Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id CF3622066F; Thu, 29 Jun 2017 18:52:25 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Thu, 29 Jun 2017 18:52:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=J4zJf2VELzvzV91 /lfEythPzw4JwGPGRuZ4o6bwRVYc=; b=j+UedUsKCJr/dkQ3d9Uk0wnaJK3yvq/ 06Y6UQyq/QeUFICaU8l+/ho0OwttYyA1ZWh48/0UKsH1GjMnfzaVHxpBIKXOJqMq SWtuEsIN3RWOoECRTOXJoa7vbN61/VUiAcovYBdUCmO0dJo/voiy409VoX7lX+HA o+NJsmDE5aBc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=J4zJf2VELzvzV91/lfEythPzw4JwGPGRuZ4o6bwRVYc=; b=Gh2vFSoU kzlddC551PdgPBfyjlpKPuqkAZJBMGPSzXrhl/0FEeM+OC7s2WSBt8ZSk3as2TIW wdLQLjrILmIG1ci2muoI3eZOXC6w4RguGScoYFTmip+RtR9sHHUal6B0Aon8YM39 OT0fWvrNiGY0rEzPcQ9ZCjQEzfTMQB2XGiLQbB1q5MDSrypz1mIgy37cdjGVrjLT bGWTHRXHPqJHppfDyhW2f0IDNadUC81i7W6bYn3oLa9QQ5odIhA5xgvS88i+eBZ+ 8H4SnZkaLkQAVx0eTihOluoIWkXl3x7RYrAnkPB2KceRF/2+SiAuY/1EOfWd+NAE okwMD5FUrpWhWg== X-ME-Sender: X-Sasl-enc: B9lDpJSizl7WUBnRiaIvu/alGsWNXaOQEofgcBusbfDc 1498776745 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 85BF5246E8; Thu, 29 Jun 2017 18:52:25 -0400 (EDT) Date: Thu, 29 Jun 2017 18:52:25 -0400 From: "Emilio G. Cota" To: =?iso-8859-1?Q?Llu=EDs?= Vilanova Cc: qemu-devel@nongnu.org, Alex =?iso-8859-1?Q?Benn=E9e?= , Richard Henderson , Peter Crosthwaite , Paolo Bonzini , Peter Maydell , "Edgar E. Iglesias" , Eduardo Habkost , Michael Walle , Laurent Vivier , Aurelien Jarno , Yongbok Kim , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Alexander Graf , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Guan Xuetao , Max Filippov , "open list:ARM" , "open list:PowerPC" Subject: Re: [PATCH v11 01/29] Pass generic CPUState to gen_intermediate_code() Message-ID: <20170629225225.GA13979@flamenco> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> <149865244195.17063.11938084353514091141.stgit@frigg.lan> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <149865244195.17063.11938084353514091141.stgit@frigg.lan> User-Agent: Mutt/1.5.24 (2015-08-30) X-TUID: Gj9MVO3L050P On Wed, Jun 28, 2017 at 15:20:42 +0300, Lluís Vilanova wrote: > Needed to implement a target-agnostic gen_intermediate_code() in the > future. > > Signed-off-by: Lluís Vilanova > Reviewed-by: David Gibson > Reviewed-by: Richard Henderson > --- (snip) > -void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb) > +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) > { > - AlphaCPU *cpu = alpha_env_get_cpu(env); > - CPUState *cs = CPU(cpu); > + CPUAlphaState *env = cpu->env_ptr; I'd keep the original variable names, i.e. cs for CPUState in this case, just like you did for a64: > -void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) > +void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) > { > - CPUState *cs = CPU(cpu); > - CPUARMState *env = &cpu->env; > + CPUARMState *env = cs->env_ptr; > + ARMCPU *cpu = arm_env_get_cpu(env); This will keep the diff size to a minimum. E. From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55375) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dQiId-0000Qx-TX for qemu-devel@nongnu.org; Thu, 29 Jun 2017 18:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dQiIZ-0003Lx-7k for qemu-devel@nongnu.org; Thu, 29 Jun 2017 18:52:35 -0400 Date: Thu, 29 Jun 2017 18:52:25 -0400 From: "Emilio G. Cota" Message-ID: <20170629225225.GA13979@flamenco> References: <149865219962.17063.10630533069463266646.stgit@frigg.lan> <149865244195.17063.11938084353514091141.stgit@frigg.lan> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <149865244195.17063.11938084353514091141.stgit@frigg.lan> Subject: Re: [Qemu-devel] [PATCH v11 01/29] Pass generic CPUState to gen_intermediate_code() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?Llu=EDs?= Vilanova Cc: qemu-devel@nongnu.org, Alex =?iso-8859-1?Q?Benn=E9e?= , Richard Henderson , Peter Crosthwaite , Paolo Bonzini , Peter Maydell , "Edgar E. Iglesias" , Eduardo Habkost , Michael Walle , Laurent Vivier , Aurelien Jarno , Yongbok Kim , Anthony Green , Chris Wulff , Marek Vasut , Stafford Horne , David Gibson , Alexander Graf , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Guan Xuetao , Max Filippov , "open list:ARM" , "open list:PowerPC" On Wed, Jun 28, 2017 at 15:20:42 +0300, Lluís Vilanova wrote: > Needed to implement a target-agnostic gen_intermediate_code() in the > future. > > Signed-off-by: Lluís Vilanova > Reviewed-by: David Gibson > Reviewed-by: Richard Henderson > --- (snip) > -void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb) > +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb) > { > - AlphaCPU *cpu = alpha_env_get_cpu(env); > - CPUState *cs = CPU(cpu); > + CPUAlphaState *env = cpu->env_ptr; I'd keep the original variable names, i.e. cs for CPUState in this case, just like you did for a64: > -void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb) > +void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb) > { > - CPUState *cs = CPU(cpu); > - CPUARMState *env = &cpu->env; > + CPUARMState *env = cs->env_ptr; > + ARMCPU *cpu = arm_env_get_cpu(env); This will keep the diff size to a minimum. E.