From: David Gibson <david@gibson.dropbear.id.au>
To: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, clg@kaod.org,
bharata@linux.vnet.ibm.com, benh@kernel.crashing.org
Subject: Re: [Qemu-devel] [PATCH v3] spapr: disable decrementer during reset
Date: Tue, 18 Jul 2017 14:46:19 +1000 [thread overview]
Message-ID: <20170718044619.GC3140@umbus.fritz.box> (raw)
In-Reply-To: <20170717041639.16137-1-nikunj@linux.vnet.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 4213 bytes --]
On Mon, Jul 17, 2017 at 09:46:39AM +0530, Nikunj A Dadhania wrote:
> Rebooting a SMP TCG guest is broken for both single/multi threaded TCG.
>
> When reset happens, all the CPUs are in halted state. First CPU is brought out
> of reset and secondary CPUs would be initialized by the guest kernel using a
> rtas call start-cpu.
>
> However, in case of TCG, decrementer interrupts keep on coming and waking the
> secondary CPUs up.
>
> These secondary CPUs would see the decrementer interrupt pending, which makes
> cpu::has_work() to bring them out of wait loop and start executing
> tcg_exec_cpu().
>
> The problem with this is all the CPUs wake up and start booting SLOF image,
> causing the following exception(4 CPUs TCG VM):
Ok, I'm still trying to understand why the behaviour on reboot is
different from the first boot. AFAICT on initial boot, the LPCR will
have DEE / PECE3 enabled. So why aren't we getting the same problem
then?
>
> [ 81.440850] reboot: Restarting system
>
> SLOF
> S
> SLOF
> SLOFLOF[0[0m **********************************************************************
> QEMU Starting
> Build Date = Mar 3 2017 13:29:19
> FW Version = git-66d250ef0fd06bb8
> [0m **********************************************************************
> QEMU Starting
> Build Date = Mar 3 2017 13:29:19
> FW Version = git-66d250ef0fd06bb8
> [0m *************************************m**********[?25l **********************************************************************
> QEMU Starting
> Build Date = Mar 3 2017 13:29:19
> FW Version = git-66d250ef0fd06bb8
> ***********************
> QEMU Starting
> Build Date = Mar 3 2017 13:29:19
> FW Version = git-66d250ef0fd06bb8
> ERROR: Flatten device tree not available!
>
> exception 300
> SRR0 = 00000000000060e4 SRR1 = 800000008000000000000000
> SPRG2 = 0000000000400000 SPRG3 = 0000000000004bd8
> ERROR: Flatten device tree not available!
>
> exception 300
> SRR0 = 00000000000060e4 SRR1 = 800000008000000000000000
> SPRG2 = 0000000000400000 SPRG3 = 0000000000004bd8
>
> During reset, disable decrementer interrupt for secondary CPUs and enable them
> when the secondary CPUs are brought online by rtas start-cpu call.
>
> Reported-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> hw/ppc/spapr_cpu_core.c | 9 +++++++++
> hw/ppc/spapr_rtas.c | 8 ++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index ea278ce..bbfe8c2 100644
> --- a/hw/ppc/spapr_cpu_core.c
> +++ b/hw/ppc/spapr_cpu_core.c
> @@ -87,6 +87,15 @@ static void spapr_cpu_reset(void *opaque)
>
> env->spr[SPR_HIOR] = 0;
>
> + /* Disable DECR for secondary cpus */
> + if (cs != first_cpu) {
> + if (env->mmu_model == POWERPC_MMU_3_00) {
> + env->spr[SPR_LPCR] &= ~LPCR_DEE;
> + } else {
> + /* P7 and P8 both have same bit for DECR */
> + env->spr[SPR_LPCR] &= ~LPCR_P8_PECE3;
> + }
> + }
> /*
> * This is a hack for the benefit of KVM PR - it abuses the SDR1
> * slot in kvm_sregs to communicate the userspace address of the
> diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
> index 94a2799..4623d1d 100644
> --- a/hw/ppc/spapr_rtas.c
> +++ b/hw/ppc/spapr_rtas.c
> @@ -174,6 +174,14 @@ static void rtas_start_cpu(PowerPCCPU *cpu_, sPAPRMachineState *spapr,
> kvm_cpu_synchronize_state(cs);
>
> env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME);
> +
> + /* Enable DECR interrupt */
> + if (env->mmu_model == POWERPC_MMU_3_00) {
> + env->spr[SPR_LPCR] |= LPCR_DEE;
> + } else {
> + /* P7 and P8 both have same bit for DECR */
> + env->spr[SPR_LPCR] |= LPCR_P8_PECE3;
> + }
> env->nip = start;
> env->gpr[3] = r3;
> cs->halted = 0;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
next prev parent reply other threads:[~2017-07-18 4:52 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-17 4:16 [Qemu-devel] [PATCH v3] spapr: disable decrementer during reset Nikunj A Dadhania
2017-07-18 4:46 ` David Gibson [this message]
2017-07-18 5:17 ` Nikunj A Dadhania
2017-07-18 5:23 ` Nikunj A Dadhania
2017-07-18 6:50 ` David Gibson
2017-07-19 3:50 ` Nikunj A Dadhania
2017-07-19 4:32 ` David Gibson
2017-09-14 6:02 ` Nikunj A Dadhania
2017-07-18 5:26 ` Nikunj A Dadhania
2017-07-18 11:01 ` Benjamin Herrenschmidt
2017-09-27 20:36 ` Cédric Le Goater
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170718044619.GC3140@umbus.fritz.box \
--to=david@gibson.dropbear.id.au \
--cc=benh@kernel.crashing.org \
--cc=bharata@linux.vnet.ibm.com \
--cc=clg@kaod.org \
--cc=nikunj@linux.vnet.ibm.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.