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diff for duplicates of <20170719113017.GH13642@arm.com>

diff --git a/a/1.txt b/N1/1.txt
index e16a564..c974300 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,7 +1,7 @@
 On Wed, Jul 19, 2017 at 04:56:38PM +0530, Anup Patel wrote:
-> On Wed, Jul 19, 2017 at 4:53 PM, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote:
+> On Wed, Jul 19, 2017 at 4:53 PM, Will Deacon <will.deacon@arm.com> wrote:
 > > On Wed, Jul 19, 2017 at 04:49:00PM +0530, Anup Patel wrote:
-> >> On Wed, Jul 19, 2017 at 4:28 PM, Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> wrote:
+> >> On Wed, Jul 19, 2017 at 4:28 PM, Robin Murphy <robin.murphy@arm.com> wrote:
 > >> > On 19/07/17 10:33, Anup Patel wrote:
 > >> >> Some of the IOMMUs (such as ARM SMMU) are capable of bypassing
 > >> >> transactions for which no IOMMU domain is configured.
diff --git a/a/content_digest b/N1/content_digest
index 6464609..d6773d7 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -4,23 +4,16 @@
  "ref\0CAALAos_o25mtphxcVE0rr9dE8YAm-os2C_HD9oDnt41ZMDP8pA@mail.gmail.com\0"
  "ref\020170719112315.GE13642@arm.com\0"
  "ref\0CAALAos8nf-d5i74J7-sAJb2o9eFj2PVDeLLVd=wun+gW1ihXSA@mail.gmail.com\0"
- "ref\0CAALAos8nf-d5i74J7-sAJb2o9eFj2PVDeLLVd=wun+gW1ihXSA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0"
- "From\0Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\0"
- "Subject\0Re: [PATCH 1/5] iommu: Add capability IOMMU_CAP_BYPASS\0"
+ "From\0will.deacon@arm.com (Will Deacon)\0"
+ "Subject\0[PATCH 1/5] iommu: Add capability IOMMU_CAP_BYPASS\0"
  "Date\0Wed, 19 Jul 2017 12:30:17 +0100\0"
- "To\0Anup Patel <anup.patel-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>\0"
- "Cc\0kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
-  Scott Branden <sbranden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
-  Linux Kernel <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  Linux IOMMU <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>
-  BCM Kernel Feedback <bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
- " Linux ARM Kernel <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "On Wed, Jul 19, 2017 at 04:56:38PM +0530, Anup Patel wrote:\n"
- "> On Wed, Jul 19, 2017 at 4:53 PM, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote:\n"
+ "> On Wed, Jul 19, 2017 at 4:53 PM, Will Deacon <will.deacon@arm.com> wrote:\n"
  "> > On Wed, Jul 19, 2017 at 04:49:00PM +0530, Anup Patel wrote:\n"
- "> >> On Wed, Jul 19, 2017 at 4:28 PM, Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> wrote:\n"
+ "> >> On Wed, Jul 19, 2017 at 4:28 PM, Robin Murphy <robin.murphy@arm.com> wrote:\n"
  "> >> > On 19/07/17 10:33, Anup Patel wrote:\n"
  "> >> >> Some of the IOMMUs (such as ARM SMMU) are capable of bypassing\n"
  "> >> >> transactions for which no IOMMU domain is configured.\n"
@@ -62,4 +55,4 @@
  "\n"
  Will
 
-6352ad308cad498d8f545ccf1f2704f3a2f8618d6b3eab48e6216e87e79fd557
+e8f8672ee8130380570a8dc7dd68d490c7dd48f5e461942b38e1130b7fb3bc19

diff --git a/a/1.txt b/N2/1.txt
index e16a564..c974300 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -1,7 +1,7 @@
 On Wed, Jul 19, 2017 at 04:56:38PM +0530, Anup Patel wrote:
-> On Wed, Jul 19, 2017 at 4:53 PM, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote:
+> On Wed, Jul 19, 2017 at 4:53 PM, Will Deacon <will.deacon@arm.com> wrote:
 > > On Wed, Jul 19, 2017 at 04:49:00PM +0530, Anup Patel wrote:
-> >> On Wed, Jul 19, 2017 at 4:28 PM, Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> wrote:
+> >> On Wed, Jul 19, 2017 at 4:28 PM, Robin Murphy <robin.murphy@arm.com> wrote:
 > >> > On 19/07/17 10:33, Anup Patel wrote:
 > >> >> Some of the IOMMUs (such as ARM SMMU) are capable of bypassing
 > >> >> transactions for which no IOMMU domain is configured.
diff --git a/a/content_digest b/N2/content_digest
index 6464609..464b907 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -4,23 +4,26 @@
  "ref\0CAALAos_o25mtphxcVE0rr9dE8YAm-os2C_HD9oDnt41ZMDP8pA@mail.gmail.com\0"
  "ref\020170719112315.GE13642@arm.com\0"
  "ref\0CAALAos8nf-d5i74J7-sAJb2o9eFj2PVDeLLVd=wun+gW1ihXSA@mail.gmail.com\0"
- "ref\0CAALAos8nf-d5i74J7-sAJb2o9eFj2PVDeLLVd=wun+gW1ihXSA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0"
- "From\0Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\0"
+ "From\0Will Deacon <will.deacon@arm.com>\0"
  "Subject\0Re: [PATCH 1/5] iommu: Add capability IOMMU_CAP_BYPASS\0"
  "Date\0Wed, 19 Jul 2017 12:30:17 +0100\0"
- "To\0Anup Patel <anup.patel-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>\0"
- "Cc\0kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
-  Scott Branden <sbranden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
-  Linux Kernel <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  Linux IOMMU <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>
-  BCM Kernel Feedback <bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
- " Linux ARM Kernel <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0"
+ "To\0Anup Patel <anup.patel@broadcom.com>\0"
+ "Cc\0Robin Murphy <robin.murphy@arm.com>"
+  Joerg Roedel <joro@8bytes.org>
+  Baptiste Reynal <b.reynal@virtualopensystems.com>
+  Alex Williamson <alex.williamson@redhat.com>
+  Scott Branden <sbranden@broadcom.com>
+  Linux Kernel <linux-kernel@vger.kernel.org>
+  Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>
+  Linux IOMMU <iommu@lists.linux-foundation.org>
+  kvm@vger.kernel.org
+ " BCM Kernel Feedback <bcm-kernel-feedback-list@broadcom.com>\0"
  "\00:1\0"
  "b\0"
  "On Wed, Jul 19, 2017 at 04:56:38PM +0530, Anup Patel wrote:\n"
- "> On Wed, Jul 19, 2017 at 4:53 PM, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote:\n"
+ "> On Wed, Jul 19, 2017 at 4:53 PM, Will Deacon <will.deacon@arm.com> wrote:\n"
  "> > On Wed, Jul 19, 2017 at 04:49:00PM +0530, Anup Patel wrote:\n"
- "> >> On Wed, Jul 19, 2017 at 4:28 PM, Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> wrote:\n"
+ "> >> On Wed, Jul 19, 2017 at 4:28 PM, Robin Murphy <robin.murphy@arm.com> wrote:\n"
  "> >> > On 19/07/17 10:33, Anup Patel wrote:\n"
  "> >> >> Some of the IOMMUs (such as ARM SMMU) are capable of bypassing\n"
  "> >> >> transactions for which no IOMMU domain is configured.\n"
@@ -62,4 +65,4 @@
  "\n"
  Will
 
-6352ad308cad498d8f545ccf1f2704f3a2f8618d6b3eab48e6216e87e79fd557
+d97a9040019390199ae2f74a73226fae53dd1a3659c1cedf431e8862aece3e70

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