From: Stephen Boyd <sboyd@codeaurora.org>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Michael Turquette <mturquette@baylibre.com>,
linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH 2/4] clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3
Date: Fri, 21 Jul 2017 13:34:18 -0700 [thread overview]
Message-ID: <20170721203418.GE19878@codeaurora.org> (raw)
In-Reply-To: <1500554409-22423-3-git-send-email-geert+renesas@glider.be>
On 07/20, Geert Uytterhoeven wrote:
> On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider
> value different from one. Extend struct rcar_gen3_cpg_pll_config to handle
> this. As all multipliers and dividers are small, table size increase
> can be kept limited by storing them in u8s instead of unsigned ints,
> which saves ca. 0.5 KiB for a generic kernel.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2017-07-21 20:34 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-20 12:40 [PATCH 0/4] clk: renesas: Add R-Car D3 support Geert Uytterhoeven
2017-07-20 12:40 ` [PATCH 1/4] clk: renesas: Add r8a77995 CPG Core Clock Definitions Geert Uytterhoeven
2017-07-21 20:34 ` Stephen Boyd
2017-07-20 12:40 ` [PATCH 2/4] clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3 Geert Uytterhoeven
2017-07-21 20:34 ` Stephen Boyd [this message]
2017-07-20 12:40 ` [PATCH 3/4] clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks Geert Uytterhoeven
2017-07-21 20:34 ` Stephen Boyd
2017-07-20 12:40 ` [PATCH 4/4] clk: renesas: cpg-mssr: Add R8A77995 support Geert Uytterhoeven
2017-07-21 20:34 ` Stephen Boyd
2017-07-24 20:09 ` Rob Herring
2017-07-24 20:09 ` Rob Herring
2017-08-17 7:23 ` [PATCH 0/4] clk: renesas: Add R-Car D3 support Geert Uytterhoeven
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