From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joerg Roedel Subject: Re: [PATCH v2 0/4] Optimise 64-bit IOVA allocations Date: Wed, 26 Jul 2017 13:08:07 +0200 Message-ID: <20170726110807.GN15833@8bytes.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Robin Murphy Cc: ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, Jonathan.Cameron-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, ray.jui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, thunder.leizhen-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: iommu@lists.linux-foundation.org Hi Robin. On Fri, Jul 21, 2017 at 12:41:57PM +0100, Robin Murphy wrote: > Hi all, > > In the wake of the ARM SMMU optimisation efforts, it seems that certain > workloads (e.g. storage I/O with large scatterlists) probably remain quite > heavily influenced by IOVA allocation performance. Separately, Ard also > reported massive performance drops for a graphical desktop on AMD Seattle > when enabling SMMUs via IORT, which we traced to dma_32bit_pfn in the DMA > ops domain getting initialised differently for ACPI vs. DT, and exposing > the overhead of the rbtree slow path. Whilst we could go around trying to > close up all the little gaps that lead to hitting the slowest case, it > seems a much better idea to simply make said slowest case a lot less slow. Do you have some numbers here? How big was the impact before these patches and how is it with the patches? Joerg From mboxrd@z Thu Jan 1 00:00:00 1970 From: joro@8bytes.org (Joerg Roedel) Date: Wed, 26 Jul 2017 13:08:07 +0200 Subject: [PATCH v2 0/4] Optimise 64-bit IOVA allocations In-Reply-To: References: Message-ID: <20170726110807.GN15833@8bytes.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Robin. On Fri, Jul 21, 2017 at 12:41:57PM +0100, Robin Murphy wrote: > Hi all, > > In the wake of the ARM SMMU optimisation efforts, it seems that certain > workloads (e.g. storage I/O with large scatterlists) probably remain quite > heavily influenced by IOVA allocation performance. Separately, Ard also > reported massive performance drops for a graphical desktop on AMD Seattle > when enabling SMMUs via IORT, which we traced to dma_32bit_pfn in the DMA > ops domain getting initialised differently for ACPI vs. DT, and exposing > the overhead of the rbtree slow path. Whilst we could go around trying to > close up all the little gaps that lead to hitting the slowest case, it > seems a much better idea to simply make said slowest case a lot less slow. Do you have some numbers here? How big was the impact before these patches and how is it with the patches? Joerg From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751481AbdGZLIL (ORCPT ); Wed, 26 Jul 2017 07:08:11 -0400 Received: from 8bytes.org ([81.169.241.247]:57948 "EHLO theia.8bytes.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750898AbdGZLIK (ORCPT ); Wed, 26 Jul 2017 07:08:10 -0400 Date: Wed, 26 Jul 2017 13:08:07 +0200 From: Joerg Roedel To: Robin Murphy Cc: iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dwmw2@infradead.org, thunder.leizhen@huawei.com, lorenzo.pieralisi@arm.com, ard.biesheuvel@linaro.org, Jonathan.Cameron@huawei.com, nwatters@codeaurora.org, ray.jui@broadcom.com Subject: Re: [PATCH v2 0/4] Optimise 64-bit IOVA allocations Message-ID: <20170726110807.GN15833@8bytes.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Robin. On Fri, Jul 21, 2017 at 12:41:57PM +0100, Robin Murphy wrote: > Hi all, > > In the wake of the ARM SMMU optimisation efforts, it seems that certain > workloads (e.g. storage I/O with large scatterlists) probably remain quite > heavily influenced by IOVA allocation performance. Separately, Ard also > reported massive performance drops for a graphical desktop on AMD Seattle > when enabling SMMUs via IORT, which we traced to dma_32bit_pfn in the DMA > ops domain getting initialised differently for ACPI vs. DT, and exposing > the overhead of the rbtree slow path. Whilst we could go around trying to > close up all the little gaps that lead to hitting the slowest case, it > seems a much better idea to simply make said slowest case a lot less slow. Do you have some numbers here? How big was the impact before these patches and how is it with the patches? Joerg