From mboxrd@z Thu Jan 1 00:00:00 1970 From: clabbe.montjoie@gmail.com (Corentin Labbe) Date: Fri, 28 Jul 2017 16:25:08 +0200 Subject: [PATCH 0/3] net-next: stmmac: support future possible different internal phy mode In-Reply-To: <20170728135544.GD32230@lunn.ch> References: <20170728092818.23419-1-clabbe.montjoie@gmail.com> <20170728135544.GD32230@lunn.ch> Message-ID: <20170728142508.GA7221@Red> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Jul 28, 2017 at 03:55:44PM +0200, Andrew Lunn wrote: > On Fri, Jul 28, 2017 at 11:28:15AM +0200, Corentin Labbe wrote: > > Hello > > > > The current way to find if the phy is internal is to compare DT phy-mode > > and emac_variant/internal_phy. > > But it will negate a possible future SoC where an external PHY use the > > same phy mode than the internal one. > > > > This patchs series adds a new way to find if the PHY is internal, via its > > compatible. > > http://elixir.free-electrons.com/linux/latest/source/drivers/of/of_mdio.c#L144 > > Since you also have "ethernet-phy-ieee802.3-c22", you won't get the > warning. But still, your device tree gives the wrong idea. > > I've probably asked this before: Does the internal PHY use a different > PHY ID in registers 2 and 3? > yes reg2: 0x0044 reg3: 0X1500 Regards From mboxrd@z Thu Jan 1 00:00:00 1970 From: Corentin Labbe Subject: Re: [PATCH 0/3] net-next: stmmac: support future possible different internal phy mode Date: Fri, 28 Jul 2017 16:25:08 +0200 Message-ID: <20170728142508.GA7221@Red> References: <20170728092818.23419-1-clabbe.montjoie@gmail.com> <20170728135544.GD32230@lunn.ch> Reply-To: clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20170728135544.GD32230-g2DYL2Zd6BY@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Andrew Lunn Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org, peppe.cavallaro-qxv4g6HH51o@public.gmane.org, alexandre.torgue-qxv4g6HH51o@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, icenowy-h8G6r0blFSE@public.gmane.org List-Id: devicetree@vger.kernel.org On Fri, Jul 28, 2017 at 03:55:44PM +0200, Andrew Lunn wrote: > On Fri, Jul 28, 2017 at 11:28:15AM +0200, Corentin Labbe wrote: > > Hello > > > > The current way to find if the phy is internal is to compare DT phy-mode > > and emac_variant/internal_phy. > > But it will negate a possible future SoC where an external PHY use the > > same phy mode than the internal one. > > > > This patchs series adds a new way to find if the PHY is internal, via its > > compatible. > > http://elixir.free-electrons.com/linux/latest/source/drivers/of/of_mdio.c#L144 > > Since you also have "ethernet-phy-ieee802.3-c22", you won't get the > warning. But still, your device tree gives the wrong idea. > > I've probably asked this before: Does the internal PHY use a different > PHY ID in registers 2 and 3? > yes reg2: 0x0044 reg3: 0X1500 Regards From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752221AbdG1OZT (ORCPT ); Fri, 28 Jul 2017 10:25:19 -0400 Received: from mail-wm0-f51.google.com ([74.125.82.51]:37377 "EHLO mail-wm0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752057AbdG1OZR (ORCPT ); Fri, 28 Jul 2017 10:25:17 -0400 Date: Fri, 28 Jul 2017 16:25:08 +0200 From: Corentin Labbe To: Andrew Lunn Cc: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, peppe.cavallaro@st.com, alexandre.torgue@st.com, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, linux-arm-kernel@lists.infradead.org, icenowy@aosc.io Subject: Re: [PATCH 0/3] net-next: stmmac: support future possible different internal phy mode Message-ID: <20170728142508.GA7221@Red> References: <20170728092818.23419-1-clabbe.montjoie@gmail.com> <20170728135544.GD32230@lunn.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170728135544.GD32230@lunn.ch> User-Agent: Mutt/1.7.2 (2016-11-26) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 28, 2017 at 03:55:44PM +0200, Andrew Lunn wrote: > On Fri, Jul 28, 2017 at 11:28:15AM +0200, Corentin Labbe wrote: > > Hello > > > > The current way to find if the phy is internal is to compare DT phy-mode > > and emac_variant/internal_phy. > > But it will negate a possible future SoC where an external PHY use the > > same phy mode than the internal one. > > > > This patchs series adds a new way to find if the PHY is internal, via its > > compatible. > > http://elixir.free-electrons.com/linux/latest/source/drivers/of/of_mdio.c#L144 > > Since you also have "ethernet-phy-ieee802.3-c22", you won't get the > warning. But still, your device tree gives the wrong idea. > > I've probably asked this before: Does the internal PHY use a different > PHY ID in registers 2 and 3? > yes reg2: 0x0044 reg3: 0X1500 Regards