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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id 2sm972042lji.5.2017.08.04.18.44.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Aug 2017 18:44:56 -0700 (PDT) Date: Sat, 5 Aug 2017 03:44:55 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Message-ID: <20170805014455.GF4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-9-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501867249-1924-9-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::242 Subject: Re: [Qemu-arm] [PATCH 8/8] target/arm: Implement new do_transaction_failed hook X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org, Richard Henderson Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: FJAH2liJFs43 On Fri, Aug 04, 2017 at 06:20:49PM +0100, Peter Maydell wrote: > Implement the new do_transaction_failed hook for ARM, which should > cause the CPU to take a prefetch abort or data abort. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/internals.h | 10 ++++++++++ > target/arm/cpu.c | 1 + > target/arm/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 54 insertions(+) > > diff --git a/target/arm/internals.h b/target/arm/internals.h > index a3adbd8..13bb001 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -471,6 +471,16 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > MMUAccessType access_type, > int mmu_idx, uintptr_t retaddr); > > +/* arm_cpu_do_transaction_failed: handle a memory system error response > + * (eg "no device/memory present at address") by raising an external abort > + * exception > + */ > +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, > + vaddr addr, unsigned size, > + MMUAccessType access_type, > + int mmu_idx, MemTxAttrs attrs, > + MemTxResult response, uintptr_t retaddr); > + > /* Call the EL change hook if one has been registered */ > static inline void arm_call_el_change_hook(ARMCPU *cpu) > { > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 05c038b..6baede0 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1670,6 +1670,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) > #else > cc->do_interrupt = arm_cpu_do_interrupt; > cc->do_unaligned_access = arm_cpu_do_unaligned_access; > + cc->do_transaction_failed = arm_cpu_do_transaction_failed; > cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; > cc->asidx_from_attrs = arm_asidx_from_attrs; > cc->vmsd = &vmstate_arm_cpu; > diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c > index 7eac272..54b6dd8 100644 > --- a/target/arm/op_helper.c > +++ b/target/arm/op_helper.c > @@ -229,6 +229,49 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi); > } > > +/* arm_cpu_do_transaction_failed: handle a memory system error response > + * (eg "no device/memory present at address") by raising an external abort > + * exception > + */ > +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, > + vaddr addr, unsigned size, > + MMUAccessType access_type, > + int mmu_idx, MemTxAttrs attrs, > + MemTxResult response, uintptr_t retaddr) > +{ > + ARMCPU *cpu = ARM_CPU(cs); > + CPUARMState *env = &cpu->env; > + uint32_t fsr, fsc; > + ARMMMUFaultInfo fi = {}; > + ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); > + > + if (retaddr) { > + /* now we have a real cpu fault */ > + cpu_restore_state(cs, retaddr); > + } > + > + /* The EA bit in syndromes and fault status registers is an > + * IMPDEF classification of external aborts. ARM implementations > + * usually use this to indicate AXI bus Decode error (0) or > + * Slave error (1); in QEMU we follow that. > + */ > + fi.ea = (response != MEMTX_DECODE_ERROR); > + > + /* The fault status register format depends on whether we're using > + * the LPAE long descriptor format, or the short descriptor format. > + */ > + if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { > + /* long descriptor form, STATUS 0b010000: synchronous ext abort */ > + fsr = (fi.ea << 12) | (1 << 9) | 0x10; > + } else { > + /* short descriptor form, FSR 0b01000 : synchronous ext abort */ > + fsr = (fi.ea << 12) | 0x8; > + } > + fsc = 0x10; > + > + deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); > +} > + > #endif /* !defined(CONFIG_USER_ONLY) */ > > uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) > -- > 2.7.4 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60381) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddo9J-0005d1-Gd for qemu-devel@nongnu.org; Fri, 04 Aug 2017 21:45:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddo9I-0006vA-LI for qemu-devel@nongnu.org; Fri, 04 Aug 2017 21:45:05 -0400 Date: Sat, 5 Aug 2017 03:44:55 +0200 From: "Edgar E. Iglesias" Message-ID: <20170805014455.GF4859@toto> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> <1501867249-1924-9-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1501867249-1924-9-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH 8/8] target/arm: Implement new do_transaction_failed hook List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , patches@linaro.org On Fri, Aug 04, 2017 at 06:20:49PM +0100, Peter Maydell wrote: > Implement the new do_transaction_failed hook for ARM, which should > cause the CPU to take a prefetch abort or data abort. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target/arm/internals.h | 10 ++++++++++ > target/arm/cpu.c | 1 + > target/arm/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 54 insertions(+) > > diff --git a/target/arm/internals.h b/target/arm/internals.h > index a3adbd8..13bb001 100644 > --- a/target/arm/internals.h > +++ b/target/arm/internals.h > @@ -471,6 +471,16 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > MMUAccessType access_type, > int mmu_idx, uintptr_t retaddr); > > +/* arm_cpu_do_transaction_failed: handle a memory system error response > + * (eg "no device/memory present at address") by raising an external abort > + * exception > + */ > +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, > + vaddr addr, unsigned size, > + MMUAccessType access_type, > + int mmu_idx, MemTxAttrs attrs, > + MemTxResult response, uintptr_t retaddr); > + > /* Call the EL change hook if one has been registered */ > static inline void arm_call_el_change_hook(ARMCPU *cpu) > { > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 05c038b..6baede0 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1670,6 +1670,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) > #else > cc->do_interrupt = arm_cpu_do_interrupt; > cc->do_unaligned_access = arm_cpu_do_unaligned_access; > + cc->do_transaction_failed = arm_cpu_do_transaction_failed; > cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug; > cc->asidx_from_attrs = arm_asidx_from_attrs; > cc->vmsd = &vmstate_arm_cpu; > diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c > index 7eac272..54b6dd8 100644 > --- a/target/arm/op_helper.c > +++ b/target/arm/op_helper.c > @@ -229,6 +229,49 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, > deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi); > } > > +/* arm_cpu_do_transaction_failed: handle a memory system error response > + * (eg "no device/memory present at address") by raising an external abort > + * exception > + */ > +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, > + vaddr addr, unsigned size, > + MMUAccessType access_type, > + int mmu_idx, MemTxAttrs attrs, > + MemTxResult response, uintptr_t retaddr) > +{ > + ARMCPU *cpu = ARM_CPU(cs); > + CPUARMState *env = &cpu->env; > + uint32_t fsr, fsc; > + ARMMMUFaultInfo fi = {}; > + ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); > + > + if (retaddr) { > + /* now we have a real cpu fault */ > + cpu_restore_state(cs, retaddr); > + } > + > + /* The EA bit in syndromes and fault status registers is an > + * IMPDEF classification of external aborts. ARM implementations > + * usually use this to indicate AXI bus Decode error (0) or > + * Slave error (1); in QEMU we follow that. > + */ > + fi.ea = (response != MEMTX_DECODE_ERROR); > + > + /* The fault status register format depends on whether we're using > + * the LPAE long descriptor format, or the short descriptor format. > + */ > + if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { > + /* long descriptor form, STATUS 0b010000: synchronous ext abort */ > + fsr = (fi.ea << 12) | (1 << 9) | 0x10; > + } else { > + /* short descriptor form, FSR 0b01000 : synchronous ext abort */ > + fsr = (fi.ea << 12) | 0x8; > + } > + fsc = 0x10; > + > + deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); > +} > + > #endif /* !defined(CONFIG_USER_ONLY) */ > > uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) > -- > 2.7.4 > >