From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris Brezillon Subject: Re: [PATCH v5 1/6] drm/vc4: Avoid using vrefresh==0 mode in DSI htotal math. Date: Wed, 9 Aug 2017 16:42:53 +0200 Message-ID: <20170809164253.59bcc002@bbrezillon> References: <20170718210510.12229-1-eric@anholt.net> <20170804105304.68e3b02a@bbrezillon> <87r2wrm3ub.fsf@eliezer.anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail.free-electrons.com (mail.free-electrons.com [62.4.15.54]) by gabe.freedesktop.org (Postfix) with ESMTP id 84BBD89D30 for ; Wed, 9 Aug 2017 14:43:05 +0000 (UTC) In-Reply-To: <87r2wrm3ub.fsf@eliezer.anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Eric Anholt Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Thierry Reding , Laurent Pinchart List-Id: dri-devel@lists.freedesktop.org TGUgRnJpLCAwNCBBdWcgMjAxNyAxNDoxNTo1NiAtMDcwMCwKRXJpYyBBbmhvbHQgPGVyaWNAYW5o b2x0Lm5ldD4gYSDDqWNyaXQgOgoKPiBCb3JpcyBCcmV6aWxsb24gPGJvcmlzLmJyZXppbGxvbkBm cmVlLWVsZWN0cm9ucy5jb20+IHdyaXRlczoKPiAKPiA+IE9uIFR1ZSwgMTggSnVsIDIwMTcgMTQ6 MDU6MDUgLTA3MDAKPiA+IEVyaWMgQW5ob2x0IDxlcmljQGFuaG9sdC5uZXQ+IHdyb3RlOgo+ID4g IAo+ID4+IFRoZSBpbmNvbWluZyBtb2RlIG1pZ2h0IGhhdmUgYSBtaXNzaW5nIHZyZWZyZXNoIGZp ZWxkIGlmIGl0IGNhbWUgZnJvbQo+ID4+IGRybU1vZGVTZXRDcnRjKCksIHdoaWNoIHRoZSBrZXJu ZWwgaXMgc3VwcG9zZWQgdG8gY2FsY3VsYXRlIHVzaW5nCj4gPj4gZHJtX21vZGVfdnJlZnJlc2go KS4gIFdlIGNvdWxkIGVpdGhlciB1c2UgdGhhdCBvciB0aGUgYWRqdXN0ZWRfbW9kZSdzCj4gPj4g b3JpZ2luYWwgdnJlZnJlc2ggdmFsdWUuCj4gPj4gCj4gPj4gSG93ZXZlciwgd2UgY2FuIG1haW50 YWluIGEgbW9yZSBleGFjdCB2cmVmcmVzaCB2YWx1ZSAobm90IGp1c3QgdGhlCj4gPj4gaW50ZWdl ciBhcHByb3hpbWF0aW9uKSwgYnkgc2NhbGluZyBieSB0aGUgcmF0aW8gb2Ygb3VyIGNsb2Nrcy4K PiA+PiAKPiA+PiB2MjogVXNlIG1hdGggc3VnZ2VzdGVkIGJ5IEFuZHJ6ZWogSGFqZGEgaW5zdGVh ZC4KPiA+PiAKPiA+PiBTaWduZWQtb2ZmLWJ5OiBFcmljIEFuaG9sdCA8ZXJpY0BhbmhvbHQubmV0 Pgo+ID4+IC0tLQo+ID4+ICBkcml2ZXJzL2dwdS9kcm0vdmM0L3ZjNF9kc2kuYyB8IDMgKystCj4g Pj4gIDEgZmlsZSBjaGFuZ2VkLCAyIGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24oLSkKPiA+PiAK PiA+PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3ZjNC92YzRfZHNpLmMgYi9kcml2ZXJz L2dwdS9kcm0vdmM0L3ZjNF9kc2kuYwo+ID4+IGluZGV4IDYyOWQzNzI2MzNlNi4uNTcyMTNmNGUz YzcyIDEwMDY0NAo+ID4+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS92YzQvdmM0X2RzaS5jCj4gPj4g KysrIGIvZHJpdmVycy9ncHUvZHJtL3ZjNC92YzRfZHNpLmMKPiA+PiBAQCAtODY2LDcgKzg2Niw4 IEBAIHN0YXRpYyBib29sIHZjNF9kc2lfZW5jb2Rlcl9tb2RlX2ZpeHVwKHN0cnVjdCBkcm1fZW5j b2RlciAqZW5jb2RlciwKPiA+PiAgCWFkanVzdGVkX21vZGUtPmNsb2NrID0gcGl4ZWxfY2xvY2tf aHogLyAxMDAwICsgMTsKPiA+PiAgCj4gPj4gIAkvKiBHaXZlbiB0aGUgbmV3IHBpeGVsIGNsb2Nr LCBhZGp1c3QgSEZQIHRvIGtlZXAgdnJlZnJlc2ggdGhlIHNhbWUuICovCj4gPj4gLQlhZGp1c3Rl ZF9tb2RlLT5odG90YWwgPSBwaXhlbF9jbG9ja19oeiAvIChtb2RlLT52cmVmcmVzaCAqIG1vZGUt PnZ0b3RhbCk7Cj4gPj4gKwlhZGp1c3RlZF9tb2RlLT5odG90YWwgPSAocGl4ZWxfY2xvY2tfaHog LyAxMDAwICogbW9kZS0+aHRvdGFsIC8KPiA+PiArCQkJCSBtb2RlLT5jbG9jayk7ICAKPiA+Cj4g PiBIbSwgSSdtIG5vdCBzdXJlIEkgdW5kZXJzdGFuZCB0aGlzLiBTaG91bGRuJ3Qgd2UgaGF2ZSBz b21ldGhpbmcgbGlrZToKPiA+Cj4gPiAJYWRqdXN0ZWRfbW9kZS0+aHRvdGFsID0gKGFkanVzdGVk X21vZGUtPmNsb2NrICogbW9kZS0+aHRvdGFsKSAvCj4gPiAJCQkJbW9kZS0+Y2xvY2s7Cj4gPgo+ ID4gSXMgdGhlcmUgYSByZWFzb24gZm9yIGRvaW5nICcrIDEnIHdoZW4geW91IGNhbGN1bGF0ZSB0 aGUgYWRqdXN0ZWQKPiA+IHBpeGVsIGNsb2NrIHJhdGUgYnV0IG5vdCBoZXJlPyAgCj4gCj4gV2Un cmUgYWN0dWFsbHkgZXhwZWN0aW5nIHRvIGdldCB3aXRoaW4gZXBzaWxvbiBvZiBwaXhlbF9jbG9j a19oeiwgYnV0IHdlCj4gaGF2ZSB0byBidW1wIG91ciBjbGtfc2V0X3JhdGUoKSB0byBhIGhpZ2hl ciB2YWx1ZSBiZWNhdXNlIHRoZSBjbG9jawo+IGRyaXZlciB3aWxsIGdpdmUgeW91IGEgYmFkIGRp dmlkZXIgaWYgeW91IGFzayBmb3IgYW55dGhpbmcgbGVzcyB0aGFuIHRoZQo+IHJhdGUgaXQgY2Fu IHByb3ZpZGUuCj4gCj4gSG93IGFib3V0IEkgZG9uJ3QgaW5jcmVtZW50IHRoZSBhZGp1c3RlZF9t b2RlLT5jbG9jayAoc2luY2UgaXQnbGwgYmUKPiB1c2Vyc3BhY2UgdmlzaWJsZSBJIHRoaW5rKSwg YW5kIGluc3RlYWQgbW92ZSB0aGF0IGFuZCB0aGUgIlJvdW5kIHVwIgo+IGNvbW1lbnQgdG8gdGhl IGNsa19zZXRfcmF0ZSgpPwoKU291bmRzIGdvb2QuCl9fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxp c3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFu L2xpc3RpbmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753304AbdHIOnG convert rfc822-to-8bit (ORCPT ); Wed, 9 Aug 2017 10:43:06 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:52423 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751972AbdHIOnF (ORCPT ); Wed, 9 Aug 2017 10:43:05 -0400 Date: Wed, 9 Aug 2017 16:42:53 +0200 From: Boris Brezillon To: Eric Anholt Cc: dri-devel@lists.freedesktop.org, Archit Taneja , Andrzej Hajda , Laurent Pinchart , Thierry Reding , linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 1/6] drm/vc4: Avoid using vrefresh==0 mode in DSI htotal math. Message-ID: <20170809164253.59bcc002@bbrezillon> In-Reply-To: <87r2wrm3ub.fsf@eliezer.anholt.net> References: <20170718210510.12229-1-eric@anholt.net> <20170804105304.68e3b02a@bbrezillon> <87r2wrm3ub.fsf@eliezer.anholt.net> X-Mailer: Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le Fri, 04 Aug 2017 14:15:56 -0700, Eric Anholt a écrit : > Boris Brezillon writes: > > > On Tue, 18 Jul 2017 14:05:05 -0700 > > Eric Anholt wrote: > > > >> The incoming mode might have a missing vrefresh field if it came from > >> drmModeSetCrtc(), which the kernel is supposed to calculate using > >> drm_mode_vrefresh(). We could either use that or the adjusted_mode's > >> original vrefresh value. > >> > >> However, we can maintain a more exact vrefresh value (not just the > >> integer approximation), by scaling by the ratio of our clocks. > >> > >> v2: Use math suggested by Andrzej Hajda instead. > >> > >> Signed-off-by: Eric Anholt > >> --- > >> drivers/gpu/drm/vc4/vc4_dsi.c | 3 ++- > >> 1 file changed, 2 insertions(+), 1 deletion(-) > >> > >> diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c > >> index 629d372633e6..57213f4e3c72 100644 > >> --- a/drivers/gpu/drm/vc4/vc4_dsi.c > >> +++ b/drivers/gpu/drm/vc4/vc4_dsi.c > >> @@ -866,7 +866,8 @@ static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder, > >> adjusted_mode->clock = pixel_clock_hz / 1000 + 1; > >> > >> /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */ > >> - adjusted_mode->htotal = pixel_clock_hz / (mode->vrefresh * mode->vtotal); > >> + adjusted_mode->htotal = (pixel_clock_hz / 1000 * mode->htotal / > >> + mode->clock); > > > > Hm, I'm not sure I understand this. Shouldn't we have something like: > > > > adjusted_mode->htotal = (adjusted_mode->clock * mode->htotal) / > > mode->clock; > > > > Is there a reason for doing '+ 1' when you calculate the adjusted > > pixel clock rate but not here? > > We're actually expecting to get within epsilon of pixel_clock_hz, but we > have to bump our clk_set_rate() to a higher value because the clock > driver will give you a bad divider if you ask for anything less than the > rate it can provide. > > How about I don't increment the adjusted_mode->clock (since it'll be > userspace visible I think), and instead move that and the "Round up" > comment to the clk_set_rate()? Sounds good.