* [PATCH] drm/i915: Apply the GTT write flush for all !llc machines
@ 2017-09-07 14:31 Chris Wilson
2017-09-07 14:48 ` ✗ Fi.CI.BAT: warning for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Chris Wilson @ 2017-09-07 14:31 UTC (permalink / raw)
To: intel-gfx
We also see the delayed GTT write issue on i915g/i915gm, so let's
presume that it is a universal problem for all llc machines, and that we
just haven't yet noticed on g33, gen4 and gen5 machines.
Testcase: igt/gem_mmap_gtt/coherency # i915gm
References: https://bugs.freedesktop.org/show_bug.cgi?id=102577
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4dffebae5601..350b761b9e91 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -694,7 +694,7 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
switch (obj->base.write_domain) {
case I915_GEM_DOMAIN_GTT:
- if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
+ if (!HAS_LLC(dev_priv)) {
intel_runtime_pm_get(dev_priv);
spin_lock_irq(&dev_priv->uncore.lock);
POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
--
2.14.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread* ✗ Fi.CI.BAT: warning for drm/i915: Apply the GTT write flush for all !llc machines
2017-09-07 14:31 [PATCH] drm/i915: Apply the GTT write flush for all !llc machines Chris Wilson
@ 2017-09-07 14:48 ` Patchwork
2017-09-07 18:23 ` [PATCH] " Ville Syrjälä
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-09-07 14:48 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Apply the GTT write flush for all !llc machines
URL : https://patchwork.freedesktop.org/series/29953/
State : warning
== Summary ==
Series 29953v1 drm/i915: Apply the GTT write flush for all !llc machines
https://patchwork.freedesktop.org/api/1.0/series/29953/revisions/1/mbox/
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail -> PASS (fi-snb-2600) fdo#100215 +1
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip -> PASS (fi-skl-x1585l) fdo#101781
pass -> SKIP (fi-cfl-s)
Subgroup basic-flip-vs-wf_vblank:
pass -> SKIP (fi-cfl-s)
Test kms_frontbuffer_tracking:
Subgroup basic:
pass -> INCOMPLETE (fi-bsw-n3050) fdo#101707
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS (fi-byt-n2820) fdo#101705
Test drv_module_reload:
Subgroup basic-reload-inject:
dmesg-fail -> DMESG-WARN (fi-cfl-s) k.org#196765
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#101707 https://bugs.freedesktop.org/show_bug.cgi?id=101707
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
k.org#196765 https://bugzilla.kernel.org/show_bug.cgi?id=196765
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:455s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:442s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:364s
fi-bsw-n3050 total:225 pass:195 dwarn:0 dfail:0 fail:0 skip:29
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:255s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:523s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:522s
fi-byt-n2820 total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:516s
fi-cfl-s total:289 pass:247 dwarn:4 dfail:0 fail:0 skip:38 time:435s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:431s
fi-glk-2a total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:616s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:444s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:426s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:429s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:508s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:473s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:515s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:597s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:601s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:530s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:473s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:538s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:517s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:446s
fi-skl-x1585l total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:517s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:556s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:401s
00f9b49384df3d7874273e1368c770cc651464df drm-tip: 2017y-09m-07d-09h-58m-50s UTC integration manifest
8936122c5693 drm/i915: Apply the GTT write flush for all !llc machines
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5608/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: Apply the GTT write flush for all !llc machines
2017-09-07 14:31 [PATCH] drm/i915: Apply the GTT write flush for all !llc machines Chris Wilson
2017-09-07 14:48 ` ✗ Fi.CI.BAT: warning for " Patchwork
@ 2017-09-07 18:23 ` Ville Syrjälä
2017-09-07 18:35 ` Chris Wilson
2017-09-07 18:45 ` [PATCH v2] " Chris Wilson
2017-09-07 19:07 ` ✗ Fi.CI.BAT: failure for drm/i915: Apply the GTT write flush for all !llc machines (rev2) Patchwork
3 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2017-09-07 18:23 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Sep 07, 2017 at 03:31:08PM +0100, Chris Wilson wrote:
> We also see the delayed GTT write issue on i915g/i915gm, so let's
> presume that it is a universal problem for all llc machines, and that we
> just haven't yet noticed on g33, gen4 and gen5 machines.
>
> Testcase: igt/gem_mmap_gtt/coherency # i915gm
That fails on my i945gm as well. mmio read before the clfush does
seem to cure it. Doing the mmio after the clflush still fails. I
wonder if there's some prefetching going on or why exactly it
behaves that way...
> References: https://bugs.freedesktop.org/show_bug.cgi?id=102577
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 4dffebae5601..350b761b9e91 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -694,7 +694,7 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
>
> switch (obj->base.write_domain) {
> case I915_GEM_DOMAIN_GTT:
> - if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
> + if (!HAS_LLC(dev_priv)) {
> intel_runtime_pm_get(dev_priv);
> spin_lock_irq(&dev_priv->uncore.lock);
> POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
There's no documented register at that offset on gen2/3.
Might be less risky to read something we know to actually exist.
> --
> 2.14.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: Apply the GTT write flush for all !llc machines
2017-09-07 18:23 ` [PATCH] " Ville Syrjälä
@ 2017-09-07 18:35 ` Chris Wilson
2017-09-07 18:47 ` Ville Syrjälä
0 siblings, 1 reply; 9+ messages in thread
From: Chris Wilson @ 2017-09-07 18:35 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Quoting Ville Syrjälä (2017-09-07 19:23:27)
> On Thu, Sep 07, 2017 at 03:31:08PM +0100, Chris Wilson wrote:
> > We also see the delayed GTT write issue on i915g/i915gm, so let's
> > presume that it is a universal problem for all llc machines, and that we
> > just haven't yet noticed on g33, gen4 and gen5 machines.
> >
> > Testcase: igt/gem_mmap_gtt/coherency # i915gm
>
> That fails on my i945gm as well. mmio read before the clfush does
> seem to cure it. Doing the mmio after the clflush still fails. I
> wonder if there's some prefetching going on or why exactly it
> behaves that way...
Hmm, I thought UC read was also a barrier for speculative prefetching.
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=102577
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> > drivers/gpu/drm/i915/i915_gem.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 4dffebae5601..350b761b9e91 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -694,7 +694,7 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
> >
> > switch (obj->base.write_domain) {
> > case I915_GEM_DOMAIN_GTT:
> > - if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
> > + if (!HAS_LLC(dev_priv)) {
> > intel_runtime_pm_get(dev_priv);
> > spin_lock_irq(&dev_priv->uncore.lock);
> > POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
>
> There's no documented register at that offset on gen2/3.
> Might be less risky to read something we know to actually exist.
Darn, those registers walking around.
i915_reg_t reg;
if (INTEL_GEN(dev_priv) >= 4)
reg = RING_ACTHD(dev_priv->engine[RCS]->mmio_base);
else
reg = ACTHD;
POSTING_READ_FW(reg);
Or we experiment with using RING_HEAD as that hasn't moved.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: Apply the GTT write flush for all !llc machines
2017-09-07 18:35 ` Chris Wilson
@ 2017-09-07 18:47 ` Ville Syrjälä
0 siblings, 0 replies; 9+ messages in thread
From: Ville Syrjälä @ 2017-09-07 18:47 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Sep 07, 2017 at 07:35:22PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2017-09-07 19:23:27)
> > On Thu, Sep 07, 2017 at 03:31:08PM +0100, Chris Wilson wrote:
> > > We also see the delayed GTT write issue on i915g/i915gm, so let's
> > > presume that it is a universal problem for all llc machines, and that we
> > > just haven't yet noticed on g33, gen4 and gen5 machines.
> > >
> > > Testcase: igt/gem_mmap_gtt/coherency # i915gm
> >
> > That fails on my i945gm as well. mmio read before the clfush does
> > seem to cure it. Doing the mmio after the clflush still fails. I
> > wonder if there's some prefetching going on or why exactly it
> > behaves that way...
>
> Hmm, I thought UC read was also a barrier for speculative prefetching.
>
> > > References: https://bugs.freedesktop.org/show_bug.cgi?id=102577
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > ---
> > > drivers/gpu/drm/i915/i915_gem.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > > index 4dffebae5601..350b761b9e91 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > @@ -694,7 +694,7 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
> > >
> > > switch (obj->base.write_domain) {
> > > case I915_GEM_DOMAIN_GTT:
> > > - if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
> > > + if (!HAS_LLC(dev_priv)) {
> > > intel_runtime_pm_get(dev_priv);
> > > spin_lock_irq(&dev_priv->uncore.lock);
> > > POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
> >
> > There's no documented register at that offset on gen2/3.
> > Might be less risky to read something we know to actually exist.
>
> Darn, those registers walking around.
>
> i915_reg_t reg;
>
> if (INTEL_GEN(dev_priv) >= 4)
> reg = RING_ACTHD(dev_priv->engine[RCS]->mmio_base);
> else
> reg = ACTHD;
> POSTING_READ_FW(reg);
>
> Or we experiment with using RING_HEAD as that hasn't moved.
Either seems to work on this machine.
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2] drm/i915: Apply the GTT write flush for all !llc machines
2017-09-07 14:31 [PATCH] drm/i915: Apply the GTT write flush for all !llc machines Chris Wilson
2017-09-07 14:48 ` ✗ Fi.CI.BAT: warning for " Patchwork
2017-09-07 18:23 ` [PATCH] " Ville Syrjälä
@ 2017-09-07 18:45 ` Chris Wilson
2017-09-07 18:50 ` Ville Syrjälä
2017-09-07 19:07 ` ✗ Fi.CI.BAT: failure for drm/i915: Apply the GTT write flush for all !llc machines (rev2) Patchwork
3 siblings, 1 reply; 9+ messages in thread
From: Chris Wilson @ 2017-09-07 18:45 UTC (permalink / raw)
To: intel-gfx
We also see the delayed GTT write issue on i915g/i915gm, so let's
presume that it is a universal problem for all !llc machines, and that we
just haven't yet noticed on g33, gen4 and gen5 machines.
v2: Use a register that exists on all platforms
Testcase: igt/gem_mmap_gtt/coherency # i915gm
References: https://bugs.freedesktop.org/show_bug.cgi?id=102577
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4dffebae5601..562c9510a7db 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -694,10 +694,10 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
switch (obj->base.write_domain) {
case I915_GEM_DOMAIN_GTT:
- if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
+ if (!HAS_LLC(dev_priv)) {
intel_runtime_pm_get(dev_priv);
spin_lock_irq(&dev_priv->uncore.lock);
- POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
+ POSTING_READ_FW(RING_HEAD(dev_priv->engine[RCS]->mmio_base));
spin_unlock_irq(&dev_priv->uncore.lock);
intel_runtime_pm_put(dev_priv);
}
--
2.14.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v2] drm/i915: Apply the GTT write flush for all !llc machines
2017-09-07 18:45 ` [PATCH v2] " Chris Wilson
@ 2017-09-07 18:50 ` Ville Syrjälä
2017-09-07 20:46 ` Chris Wilson
0 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2017-09-07 18:50 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Sep 07, 2017 at 07:45:20PM +0100, Chris Wilson wrote:
> We also see the delayed GTT write issue on i915g/i915gm, so let's
> presume that it is a universal problem for all !llc machines, and that we
> just haven't yet noticed on g33, gen4 and gen5 machines.
>
> v2: Use a register that exists on all platforms
>
> Testcase: igt/gem_mmap_gtt/coherency # i915gm
> References: https://bugs.freedesktop.org/show_bug.cgi?id=102577
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 4dffebae5601..562c9510a7db 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -694,10 +694,10 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
>
> switch (obj->base.write_domain) {
> case I915_GEM_DOMAIN_GTT:
> - if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
> + if (!HAS_LLC(dev_priv)) {
> intel_runtime_pm_get(dev_priv);
> spin_lock_irq(&dev_priv->uncore.lock);
> - POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
> + POSTING_READ_FW(RING_HEAD(dev_priv->engine[RCS]->mmio_base));
> spin_unlock_irq(&dev_priv->uncore.lock);
> intel_runtime_pm_put(dev_priv);
> }
> --
> 2.14.1
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2] drm/i915: Apply the GTT write flush for all !llc machines
2017-09-07 18:50 ` Ville Syrjälä
@ 2017-09-07 20:46 ` Chris Wilson
0 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2017-09-07 20:46 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Quoting Ville Syrjälä (2017-09-07 19:50:13)
> On Thu, Sep 07, 2017 at 07:45:20PM +0100, Chris Wilson wrote:
> > We also see the delayed GTT write issue on i915g/i915gm, so let's
> > presume that it is a universal problem for all !llc machines, and that we
> > just haven't yet noticed on g33, gen4 and gen5 machines.
> >
> > v2: Use a register that exists on all platforms
> >
> > Testcase: igt/gem_mmap_gtt/coherency # i915gm
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=102577
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Seems to be doing the trick nicely. i915gm has settled down now for a
long run to hunt for coherency issues, and bsw/bxt are still happy.
Pushed, thanks for the review, especially catching ACTHD migrated.
-Chris
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Apply the GTT write flush for all !llc machines (rev2)
2017-09-07 14:31 [PATCH] drm/i915: Apply the GTT write flush for all !llc machines Chris Wilson
` (2 preceding siblings ...)
2017-09-07 18:45 ` [PATCH v2] " Chris Wilson
@ 2017-09-07 19:07 ` Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2017-09-07 19:07 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Apply the GTT write flush for all !llc machines (rev2)
URL : https://patchwork.freedesktop.org/series/29953/
State : failure
== Summary ==
Series 29953v2 drm/i915: Apply the GTT write flush for all !llc machines
https://patchwork.freedesktop.org/api/1.0/series/29953/revisions/2/mbox/
Test chamelium:
Subgroup dp-edid-read:
pass -> FAIL (fi-kbl-7500u)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail -> PASS (fi-snb-2600) fdo#100215
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass -> SKIP (fi-cfl-s) fdo#102294
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:461s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:441s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:361s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:564s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:254s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:525s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:532s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:525s
fi-cfl-s total:289 pass:249 dwarn:4 dfail:0 fail:0 skip:36 time:464s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:434s
fi-glk-2a total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:609s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:454s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:427s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:436s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:508s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:480s
fi-kbl-7500u total:289 pass:263 dwarn:1 dfail:0 fail:1 skip:24 time:511s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:594s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:604s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:530s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:474s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:541s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:522s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:445s
fi-skl-x1585l total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:510s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:563s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:1 skip:39 time:406s
2300dd9c44b8764024d751604328f1e29966f444 drm-tip: 2017y-09m-07d-16h-59m-41s UTC integration manifest
ab7e50563dc5 drm/i915: Apply the GTT write flush for all !llc machines
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5611/
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-09-07 20:46 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-09-07 14:31 [PATCH] drm/i915: Apply the GTT write flush for all !llc machines Chris Wilson
2017-09-07 14:48 ` ✗ Fi.CI.BAT: warning for " Patchwork
2017-09-07 18:23 ` [PATCH] " Ville Syrjälä
2017-09-07 18:35 ` Chris Wilson
2017-09-07 18:47 ` Ville Syrjälä
2017-09-07 18:45 ` [PATCH v2] " Chris Wilson
2017-09-07 18:50 ` Ville Syrjälä
2017-09-07 20:46 ` Chris Wilson
2017-09-07 19:07 ` ✗ Fi.CI.BAT: failure for drm/i915: Apply the GTT write flush for all !llc machines (rev2) Patchwork
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