From mboxrd@z Thu Jan 1 00:00:00 1970 From: andrew@lunn.ch (Andrew Lunn) Date: Mon, 11 Sep 2017 22:19:20 +0200 Subject: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs In-Reply-To: <20170911190850.GA2291@Red> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> <20170908071156.5115-11-clabbe.montjoie@gmail.com> <20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red> <20170908140020.GC25219@lunn.ch> <20170908140832.GB3037@Red> <20170908141736.GF25219@lunn.ch> <20170908142825.GC3037@Red> <20170911161124.GD27599@lunn.ch> <20170911190850.GA2291@Red> Message-ID: <20170911201920.GA5983@lunn.ch> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > Even with CLK_BUS_EPHY/RST_BUS_EPHY enabled, the MAC reset timeout. > So no the CLK/RST are really for the PHY. Thanks for trying that. You said it was probably during scanning of the bus it times out. What address is causing the timeout? 0 or 1? If the internal bus can only have one PHY on it, maybe we need to set bus->phy_mask to 0x1? Andrew From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andrew Lunn Subject: Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs Date: Mon, 11 Sep 2017 22:19:20 +0200 Message-ID: <20170911201920.GA5983@lunn.ch> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> <20170908071156.5115-11-clabbe.montjoie@gmail.com> <20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red> <20170908140020.GC25219@lunn.ch> <20170908140832.GB3037@Red> <20170908141736.GF25219@lunn.ch> <20170908142825.GC3037@Red> <20170911161124.GD27599@lunn.ch> <20170911190850.GA2291@Red> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20170911190850.GA2291@Red> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Corentin Labbe Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, linux-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org, catalin.marinas-5wv7dgnIgG8@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, peppe.cavallaro-qxv4g6HH51o@public.gmane.org, alexandre.torgue-qxv4g6HH51o@public.gmane.org, f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org > Even with CLK_BUS_EPHY/RST_BUS_EPHY enabled, the MAC reset timeout. > So no the CLK/RST are really for the PHY. Thanks for trying that. You said it was probably during scanning of the bus it times out. What address is causing the timeout? 0 or 1? If the internal bus can only have one PHY on it, maybe we need to set bus->phy_mask to 0x1? Andrew -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751160AbdIKUTf (ORCPT ); Mon, 11 Sep 2017 16:19:35 -0400 Received: from vps0.lunn.ch ([178.209.37.122]:37507 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750853AbdIKUTd (ORCPT ); Mon, 11 Sep 2017 16:19:33 -0400 Date: Mon, 11 Sep 2017 22:19:20 +0200 From: Andrew Lunn To: Corentin Labbe Cc: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, f.fainelli@gmail.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs Message-ID: <20170911201920.GA5983@lunn.ch> References: <20170908071156.5115-1-clabbe.montjoie@gmail.com> <20170908071156.5115-11-clabbe.montjoie@gmail.com> <20170908130520.GA11248@lunn.ch> <20170908132632.GA3037@Red> <20170908140020.GC25219@lunn.ch> <20170908140832.GB3037@Red> <20170908141736.GF25219@lunn.ch> <20170908142825.GC3037@Red> <20170911161124.GD27599@lunn.ch> <20170911190850.GA2291@Red> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170911190850.GA2291@Red> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Even with CLK_BUS_EPHY/RST_BUS_EPHY enabled, the MAC reset timeout. > So no the CLK/RST are really for the PHY. Thanks for trying that. You said it was probably during scanning of the bus it times out. What address is causing the timeout? 0 or 1? If the internal bus can only have one PHY on it, maybe we need to set bus->phy_mask to 0x1? Andrew