From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Don't rmw PIPESTAT enable bits
Date: Fri, 15 Sep 2017 13:03:36 +0300 [thread overview]
Message-ID: <20170915100336.GJ4914@intel.com> (raw)
In-Reply-To: <150542145715.19729.4091797475170950711@mail.alporthouse.com>
On Thu, Sep 14, 2017 at 09:37:37PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2017-09-14 16:17:31)
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > i830 seems to occasionally forget the PIPESTAT enable bits when
> > we read the register. These aren't the only registers on i830 that
> > have problems with RMW, as reading the double buffered plane
> > registers returns the latched value rather than the last written
> > value. So something similar is perhaps going on with PIPESTAT.
> >
> > This corruption results on vblank interrupts occasionally turning off
> > on their own, which leads to vblank timeouts and generally a stuck
> > display subsystem.
> >
> > So let's not RMW the pipestat enable bits, and instead use the cached
> > copy we have around.
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Well it didn't make my 845g any worse. Still has
>
> [ 245.683349] [drm:pipe_config_err] *ERROR* mismatch in base.adjusted_mode.flags (2) (expected 0, found 2)
> [ 245.683382] [drm:pipe_config_err] *ERROR* mismatch in base.adjusted_mode.flags (8) (expected 0, found 8)
> [ 245.683427] pipe state doesn't match!
>
> if you are interested.
That's a bit odd. Even if the mode originally doesn't have any
hsync/vsync flags intel_modeset_pipe_config() should give it some.
So I can't immediately see how we could manage to get there with
expected==0.
>
> How occasional and which test in particular hits the issue?
It's been a few months but IIRC I was just running xonotic when I
hit the problem. It was pretty good at hitting it. Prior to the fix
I had to rewrite PIPESTAT several times to make it through the
the-big-keybench demo. I don't recall anymore if I hit it with
anything else.
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2017-09-15 10:03 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-14 15:17 [PATCH] drm/i915: Don't rmw PIPESTAT enable bits Ville Syrjala
2017-09-14 16:04 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-09-14 20:37 ` [PATCH] " Chris Wilson
2017-09-15 10:03 ` Ville Syrjälä [this message]
2017-09-25 14:05 ` Ville Syrjälä
2017-09-25 14:10 ` Chris Wilson
2017-09-14 21:20 ` ✗ Fi.CI.IGT: failure for " Patchwork
2017-09-25 10:33 ` [PATCH] " Imre Deak
2017-09-25 13:53 ` Ville Syrjälä
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170915100336.GJ4914@intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=chris@chris-wilson.co.uk \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.