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Date:   Fri, 15 Sep 2017 15:19:46 +0200
From:   Fredrik Noring <noring@nocrew.org>
To:     "Maciej W. Rozycki" <macro@imgtec.com>
Cc:     linux-mips@linux-mips.org
Subject: Re: [PATCH] MIPS: Add basic R5900 support
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Hi Maciej,

>  I wonder if FS=1 hardwired also means the Underflow exception cannot 
> happen.  As the corresponding Cause and Enable bits cannot be set together 
> or an FPE exception will happen right away, and the Unimplemented 
> Operation exception is uncoditional so we need to leave it out, can you 
> please also try these masks in turns:
> 
> 	      " li   %1,0x0001f07c\n"
> 
> and:
> 
> 	      " li   %1,0x00000f80\n"
> 
> This will reveal if any of the Cause, Enable or Flag bits are hardwired.

The result is:

	FCSR 0x0001f07c old: 01000001, new: 0101c079
	FCSR 0x00000f80 old: 01000001, new: 01000001

I was looking for information on GCC for R5900 and found

https://gcc.gnu.org/ml/gcc-patches/2013-01/msg00658.html

where you and Jürgen Urban discuss this topic. Jürgen cites some FPU details
from the Emotion Engine core user's manual that is very helpful, in addition
to mentioning TX79 differences.

Fredrik