From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751866AbdIUTvE (ORCPT ); Thu, 21 Sep 2017 15:51:04 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:34772 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751729AbdIUTvC (ORCPT ); Thu, 21 Sep 2017 15:51:02 -0400 Date: Thu, 21 Sep 2017 12:50:58 -0700 From: "Paul E. McKenney" To: "Guilherme G. Piccoli" Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, corbet@lwn.net Subject: Re: [PATCH v2] Documentation: rewrite confusing statement about memory barriers Reply-To: paulmck@linux.vnet.ibm.com References: <20170921192901.19206-1-gpiccoli@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170921192901.19206-1-gpiccoli@linux.vnet.ibm.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 x-cbid: 17092119-0008-0000-0000-0000028424B5 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007774; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000231; SDB=6.00920371; UDB=6.00462470; IPR=6.00700593; BA=6.00005601; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017239; XFM=3.00000015; UTC=2017-09-21 19:50:59 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17092119-0009-0000-0000-000036C6FCFE Message-Id: <20170921195058.GM3521@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-09-21_05:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1709210267 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 21, 2017 at 04:29:01PM -0300, Guilherme G. Piccoli wrote: > In this specific portion of the write memory barriers description, > the documentation mentions sequential order of stores, which is > confusing since sequential ordering is not guaranteed. > > This patch tries to improve the doc in order to avoid any > mis-understanding. > > Cc: Paul E. McKenney > Signed-off-by: Guilherme G. Piccoli Good catch, and you are quite correct, a write barrier orders only before and after itself, doing nothing to impose order on preceding writes among themselves. Applied, thank you! Thanx, Paul > --- > > v2: added Paul in CC. > > Documentation/memory-barriers.txt | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt > index b759a60624fd..a4bbbd1b63a0 100644 > --- a/Documentation/memory-barriers.txt > +++ b/Documentation/memory-barriers.txt > @@ -383,8 +383,8 @@ Memory barriers come in four basic varieties: > to have any effect on loads. > > A CPU can be viewed as committing a sequence of store operations to the > - memory system as time progresses. All stores before a write barrier will > - occur in the sequence _before_ all the stores after the write barrier. > + memory system as time progresses. All stores _before_ a write barrier > + will occur _before_ all the stores after the write barrier. > > [!] Note that write barriers should normally be paired with read or data > dependency barriers; see the "SMP barrier pairing" subsection. > -- > 2.14.1 >