From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matthias Kaehlcke Subject: Re: [PATCH v2 2/8] drm/rockchip/dsi: add dual mipi channel support Date: Tue, 26 Sep 2017 18:25:07 -0700 Message-ID: <20170927012507.GK173745@google.com> References: <1506412523-1766-1-git-send-email-nickey.yang@rock-chips.com> <1506412523-1766-2-git-send-email-nickey.yang@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1506412523-1766-2-git-send-email-nickey.yang@rock-chips.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Nickey Yang Cc: mark.rutland@arm.com, bivvy.bi@rock-chips.com, hl@rock-chips.com, briannorris@chromium.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, robh+dt@kernel.org, zyw@rock-chips.com, xbl@rock-chips.com List-Id: linux-rockchip.vger.kernel.org SGkgTmlja2V5LAoKcGxlYXNlIHNlZSBteSBjb21tZW50IGlubGluZS4KCihOb3RlOiBJJ20gbm8g ZXhwb3J0IG9uIE1JUEkgRFNJIGluIGdlbmVyYWwgb3IgdGhpcyBkcml2ZXIvY29udHJvbGxlcgpp biBwYXJ0aWN1bGFyLCBteSByZXZpZXdzIG9mIHRoaXMgZHJpdmVyIGFyZSBtb3JlIGZvY3Vzc2Vk IG9uIEMgYW5kCmdlbmVyaWMga2VybmVsIHN0dWZmLCB0aGFuIG9uIHRoZSBkZXRhaWxzIG9mIHRo ZSBpbnRlcmFjdGlvbiB3aXRoIHRoZQpjb250cm9sbGVyKQoKRWwgVHVlLCBTZXAgMjYsIDIwMTcg YXQgMDM6NTU6MTdQTSArMDgwMCBOaWNrZXkgWWFuZyBoYSBkaXQ6Cgo+IFRoaXMgcGF0Y2ggYWRk IGR1YWwgbWlwaSBjaGFubmVsIHN1cHBvcnQ6Cj4gMS5hZGQgZGVmaW5pdGlvbiBvZiBkc2kxIHJl Z2lzdGVyIGFuZCBncmYgb3BlcmF0aW9uLgo+IDIuZHNpMCBhbmQgZHNpMSB3aWxsIHdvcmsgaW4g bWFzdGVyIGFuZCBzbGF2ZSBtb2RlCj4gd2hlbiBkcml2aW5nIGR1YWwgbWlwaSBwYW5lbC4KPiAK PiBTaWduZWQtb2ZmLWJ5OiBOaWNrZXkgWWFuZyA8bmlja2V5LnlhbmdAcm9jay1jaGlwcy5jb20+ Cj4gLS0tCj4gIGRyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jICAgICAgfCAz OTAgKysrKysrKysrKysrKysrKysrKystLS0tLS0tLQo+ICBkcml2ZXJzL2dwdS9kcm0vcm9ja2No aXAvcm9ja2NoaXBfZHJtX2Rydi5oIHwgICAxICsKPiAgZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlw L3JvY2tjaGlwX2RybV92b3AuYyB8ICAgMiArCj4gIGRyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9y b2NrY2hpcF9kcm1fdm9wLmggfCAgIDMgKwo+ICA0IGZpbGVzIGNoYW5nZWQsIDI5MiBpbnNlcnRp b25zKCspLCAxMDQgZGVsZXRpb25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry bS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL2R3LW1p cGktZHNpLmMKPiBpbmRleCBjOTMzYTNhLi4xOTEwMzdjIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMv Z3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL3Jv Y2tjaGlwL2R3LW1pcGktZHNpLmMKPiBAQCAtMzksOCArMzksNTggQEAKPiAgI2RlZmluZSBSSzMz OTlfRFNJMV9TRUxfVk9QX0xJVAkJQklUKDQpCj4gIAo+ICAvKiBkaXNhYmxlIHR1cm5yZXF1ZXN0 LCB0dXJuZGlzYWJsZSwgZm9yY2V0eHN0b3Btb2RlLCBmb3JjZXJ4bW9kZSAqLwo+IC0jZGVmaW5l IFJLMzM5OV9HUkZfU09DX0NPTjIyCQkweDYyNTgKPiAtI2RlZmluZSBSSzMzOTlfR1JGX0RTSV9N T0RFCQkweGZmZmYwMDAwCj4gKyNkZWZpbmUgUkszMzk5X0dSRl9TT0NfQ09OMjIJCQkweDYyNTgK PiArI2RlZmluZSBEUEhZX1RYMF9UVVJOUkVRVUVTVF9TRVQJCSgoMHhmIDw8IDEyKSA8PCAxNikK PiArI2RlZmluZSBEUEhZX1RYMF9UVVJOUkVRVUVTVF9ESVNBQkxFCQkoMHgwIDw8IDEyKQo+ICsj ZGVmaW5lIERQSFlfVFgwX1RVUk5SRVFVRVNUX0VOQUJMRQkJKDB4ZiA8PCAxMikKPiArI2RlZmlu ZSBEUEhZX1RYMF9UVVJORElTQUJMRV9TRVQJCSgoMHhmIDw8IDgpIDw8IDE2KQo+ICsjZGVmaW5l IERQSFlfVFgwX1RVUk5ESVNBQkxFX0RJU0FCTEUJCSgweDAgPDwgOCkKPiArI2RlZmluZSBEUEhZ X1RYMF9UVVJORElTQUJMRV9FTkFCTEUJCSgweGYgPDwgOCkKPiArI2RlZmluZSBEUEhZX1RYMF9G T1JDRVRYU1RPUE1PREVfU0VUCQkoKDB4ZiA8PCA0KSA8PCAxNikKPiArI2RlZmluZSBEUEhZX1RY MF9GT1JDRVRYU1RPUE1PREVfRElTQUJMRQkoMHgwIDw8IDQpCj4gKyNkZWZpbmUgRFBIWV9UWDBf Rk9SQ0VUWFNUT1BNT0RFX0VOQUJMRQkJKDB4ZiA8PCA0KQo+ICsjZGVmaW5lIERQSFlfVFgwX0ZP UkNFVFJYTU9ERV9TRVQJCSgoMHhmIDw8IDApIDw8IDE2KQo+ICsjZGVmaW5lIERQSFlfVFgwX0ZP UkNFVFJYTU9ERV9ESVNBQkxFCQkweDAKPiArI2RlZmluZSBEUEhZX1RYMF9GT1JDRVRSWE1PREVf RU5BQkxFCQkweGYKPiArI2RlZmluZSBSSzMzOTlfR1JGX0RTSV9NT0RFCQkJKChEUEhZX1RYMF9U VVJOUkVRVUVTVF9TRVQgfCBcCj4gKwkJCQkJCSBEUEhZX1RYMF9UVVJORElTQUJMRV9TRVQgfCBc Cj4gKwkJCQkJCSBEUEhZX1RYMF9GT1JDRVRYU1RPUE1PREVfU0VUIHwgXAo+ICsJCQkJCQkgRFBI WV9UWDBfRk9SQ0VUUlhNT0RFX1NFVCkgfCBcCj4gKwkJCQkJCSAoRFBIWV9UWDBfVFVSTlJFUVVF U1RfRElTQUJMRSB8IFwKPiArCQkJCQkJIERQSFlfVFgwX1RVUk5ESVNBQkxFX0RJU0FCTEUgfCBc Cj4gKwkJCQkJCSBEUEhZX1RYMF9GT1JDRVRYU1RPUE1PREVfRElTQUJMRSB8IFwKPiArCQkJCQkJ IERQSFlfVFgwX0ZPUkNFVFJYTU9ERV9ESVNBQkxFKSkKPiArCj4gKwo+ICsvKiBkaXNhYmxlIHR1 cm5kaXNhYmxlLCBmb3JjZXR4c3RvcG1vZGUsIGZvcmNlcnhtb2RlLCBlbmFibGUgKi8KPiArI2Rl ZmluZSBSSzMzOTlfR1JGX1NPQ19DT04yMwkJCTB4NjI1Ywo+ICsjZGVmaW5lIERQSFlfVFgxUlgx X1RVUk5ESVNBQkxFX1NFVAkJKCgweGYgPDwgMTIpIDw8IDE2KQo+ICsjZGVmaW5lIERQSFlfVFgx UlgxX1RVUk5ESVNBQkxFX0RJU0FCTEUJCSgweDAgPDwgMTIpCj4gKyNkZWZpbmUgRFBIWV9UWDFS WDFfVFVSTkRJU0FCTEVfRU5BQkxFCQkoMHhmIDw8IDEyKQo+ICsjZGVmaW5lIERQSFlfVFgxUlgx X0ZPUkNFVFhTVE9QTU9ERV9TRVQJCSgoMHhmIDw8IDgpIDw8IDE2KQo+ICsjZGVmaW5lIERQSFlf VFgxUlgxX0ZPUkNFVFhTVE9QTU9ERV9ESVNBQkxFCSgweDAgPDwgOCkKPiArI2RlZmluZSBEUEhZ X1RYMVJYMV9GT1JDRVRYU1RPUE1PREVfRU5BQkxFCSgweGYgPDwgOCkKPiArI2RlZmluZSBEUEhZ X1RYMVJYMV9GT1JDRVJYTU9ERV9TRVQJCSgoMHhmIDw8IDQpIDw8IDE2KQo+ICsjZGVmaW5lIERQ SFlfVFgxUlgxX0ZPUkNFUlhNT0RFX0RJU0FCTEUJCSgweDAgPDwgNCkKPiArI2RlZmluZSBEUEhZ X1RYMVJYMV9GT1JDRVJYTU9ERV9FTkFCTEUJCSgweGYgPDwgNCkKPiArI2RlZmluZSBEUEhZX1RY MVJYMV9FTkFCTEVfU0VUCQkJKCgweGYgPDwgMCkgPDwgMTYpCj4gKyNkZWZpbmUgRFBIWV9UWDFS WDFfRU5BQkxFX0RJU0FCTEUJCTB4MAo+ICsjZGVmaW5lIERQSFlfVFgxUlgxX0VOQUJMRV9FTkFC TEUJCTB4Zgo+ICsjZGVmaW5lIFJLMzM5OV9HUkZfRFNJMV9NT0RFCQkJKChEUEhZX1RYMVJYMV9U VVJORElTQUJMRV9TRVQgfCBcCj4gKwkJCQkJCSBEUEhZX1RYMVJYMV9GT1JDRVRYU1RPUE1PREVf U0VUIHwgXAo+ICsJCQkJCQkgRFBIWV9UWDFSWDFfRk9SQ0VSWE1PREVfU0VUIHwgXAo+ICsJCQkJ CQkgRFBIWV9UWDFSWDFfRU5BQkxFX1NFVCkgfCBcCj4gKwkJCQkJCSAoRFBIWV9UWDBfVFVSTlJF UVVFU1RfRElTQUJMRSB8IFwKPiArCQkJCQkJIERQSFlfVFgwX1RVUk5ESVNBQkxFX0RJU0FCTEUg fCBcCj4gKwkJCQkJCSBEUEhZX1RYMF9GT1JDRVRYU1RPUE1PREVfRElTQUJMRSB8IFwKPiArCQkJ CQkJIERQSFlfVFgwX0ZPUkNFVFJYTU9ERV9ESVNBQkxFKSkKPiArI2RlZmluZSBSSzMzOTlfR1JG X0RTSTFfRU5BQkxFCQkJKChEUEhZX1RYMVJYMV9FTkFCTEVfU0VUIHwgXAo+ICsJCQkJCQkgIERQ SFlfVFgxUlgxX0VOQUJMRV9FTkFCTEUpKQo+ICsKPiArI2RlZmluZSBSSzMzOTlfR1JGX1NPQ19D T04yNAkJMHg2MjYwCj4gKyNkZWZpbmUgUkszMzk5X1RYUlhfTUFTVEVSU0xBVkVaCUJJVCg3KQo+ ICsjZGVmaW5lIFJLMzM5OV9UWFJYX0VOQUJMRUNMSwkJQklUKDYpCj4gKyNkZWZpbmUgUkszMzk5 X1RYUlhfQkFTRURJUgkJQklUKDUpCj4gIAo+ICAjZGVmaW5lIERTSV9WRVJTSU9OCQkJMHgwMAo+ ICAjZGVmaW5lIERTSV9QV1JfVVAJCQkweDA0Cj4gQEAgLTMwNCw2ICszNTQsMTMgQEAgc3RydWN0 IGR3X21pcGlfZHNpX3BsYXRfZGF0YSB7Cj4gIAl1MzIgZ3JmX3N3aXRjaF9yZWc7Cj4gIAl1MzIg Z3JmX2RzaTBfbW9kZTsKPiAgCXUzMiBncmZfZHNpMF9tb2RlX3JlZzsKPiArCXUzMiBncmZfZHNp MV9tb2RlOwo+ICsJdTMyIGdyZl9kc2kxX2VuYWJsZTsKPiArCXUzMiBncmZfZHNpMV9tb2RlX3Jl ZzE7Cj4gKwl1MzIgZHNpMV9iYXNlZGlyOwo+ICsJdTMyIGRzaTFfbWFzdGVyc2xhdmV6Owo+ICsJ dTMyIGRzaTFfZW5hYmxlY2xrOwo+ICsJdTMyIGdyZl9kc2kxX21vZGVfcmVnMjsKPiAgCXVuc2ln bmVkIGludCBmbGFnczsKPiAgCXVuc2lnbmVkIGludCBtYXhfZGF0YV9sYW5lczsKPiAgfTsKPiBA QCAtMzIyLDYgKzM3OSwxMCBAQCBzdHJ1Y3QgZHdfbWlwaV9kc2kgewo+ICAJc3RydWN0IGNsayAq cGNsazsKPiAgCXN0cnVjdCBjbGsgKnBoeV9jZmdfY2xrOwo+ICAKPiArCS8qIGR1YWwtY2hhbm5l bCAqLwo+ICsJc3RydWN0IGR3X21pcGlfZHNpICptYXN0ZXI7Cj4gKwlzdHJ1Y3QgZHdfbWlwaV9k c2kgKnNsYXZlOwo+ICsKPiAgCWludCBkcG1zX21vZGU7Cj4gIAl1bnNpZ25lZCBpbnQgbGFuZV9t YnBzOyAvKiBwZXIgbGFuZSAqLwo+ICAJdTMyIGNoYW5uZWw7Cj4gQEAgLTU3NCw2ICs2MzUsNyBA QCBzdGF0aWMgaW50IGR3X21pcGlfZHNpX2dldF9sYW5lX2JwcyhzdHJ1Y3QgZHdfbWlwaV9kc2kg KmRzaSwKPiAgCXVuc2lnbmVkIGludCBtYXhfbWJwcyA9IGRwdGRpbl9tYXBbQVJSQVlfU0laRShk cHRkaW5fbWFwKSAtIDFdLm1heF9tYnBzOwo+ICAJaW50IGJwcDsKPiAgCXVuc2lnbmVkIGxvbmcg YmVzdF9mcmVxID0gMDsKPiArCWludCBsYW5lcyA9IGRzaS0+bGFuZXM7Cj4gIAl1bnNpZ25lZCBs b25nIGZ2Y29fbWluLCBmdmNvX21heCwgZmluLCBmb3V0Owo+ICAJdW5zaWduZWQgaW50IG1pbl9w cmVkaXYsIG1heF9wcmVkaXY7Cj4gIAl1bnNpZ25lZCBpbnQgX3ByZWRpdiwgdW5pbml0aWFsaXpl ZF92YXIoYmVzdF9wcmVkaXYpOwo+IEBAIC01ODcsMTAgKzY0OSwxMyBAQCBzdGF0aWMgaW50IGR3 X21pcGlfZHNpX2dldF9sYW5lX2JwcyhzdHJ1Y3QgZHdfbWlwaV9kc2kgKmRzaSwKPiAgCQlyZXR1 cm4gYnBwOwo+ICAJfQo+ICAKPiArCWlmIChkc2ktPnNsYXZlIHx8IGRzaS0+bWFzdGVyKQo+ICsJ CWxhbmVzID0gZHNpLT5sYW5lcyAqIDI7Cj4gKwo+ICAJbXBjbGsgPSBESVZfUk9VTkRfVVAobW9k ZS0+Y2xvY2ssIE1TRUNfUEVSX1NFQyk7Cj4gIAlpZiAobXBjbGspIHsKPiAgCQkvKiB0YWtlIDEg LyAwLjgsIHNpbmNlIG1icHMgbXVzdCBiaWcgdGhhbiBiYW5kd2lkdGggb2YgUkdCICovCj4gLQkJ dG1wID0gbXBjbGsgKiAoYnBwIC8gZHNpLT5sYW5lcykgKiAxMCAvIDg7Cj4gKwkJdG1wID0gbXBj bGsgKiAoYnBwIC8gbGFuZXMpICogMTAgLyA4Owo+ICAJCWlmICh0bXAgPCBtYXhfbWJwcykKPiAg CQkJdGFyZ2V0X21icHMgPSB0bXA7Cj4gIAkJZWxzZQo+IEBAIC02NTMsMTcgKzcxOCwyNiBAQCBz dGF0aWMgaW50IGR3X21pcGlfZHNpX2hvc3RfYXR0YWNoKHN0cnVjdCBtaXBpX2RzaV9ob3N0ICpo b3N0LAo+ICAJCQkJICAgc3RydWN0IG1pcGlfZHNpX2RldmljZSAqZGV2aWNlKQo+ICB7Cj4gIAlz dHJ1Y3QgZHdfbWlwaV9kc2kgKmRzaSA9IGhvc3RfdG9fZHNpKGhvc3QpOwo+ICsJaW50IGxhbmVz ID0gZHNpLT5zbGF2ZSA/IGRldmljZS0+bGFuZXMgLyAyIDogZGV2aWNlLT5sYW5lczsKPiAgCj4g LQlpZiAoZGV2aWNlLT5sYW5lcyA+IGRzaS0+cGRhdGEtPm1heF9kYXRhX2xhbmVzKSB7Cj4gKwlp ZiAobGFuZXMgPiBkc2ktPnBkYXRhLT5tYXhfZGF0YV9sYW5lcykgewo+ICAJCWRldl9lcnIoZHNp LT5kZXYsICJ0aGUgbnVtYmVyIG9mIGRhdGEgbGFuZXMoJXUpIGlzIHRvbyBtYW55XG4iLAo+IC0J CQlkZXZpY2UtPmxhbmVzKTsKPiArCQkJbGFuZXMpOwo+ICAJCXJldHVybiAtRUlOVkFMOwo+ICAJ fQo+ICAKPiAtCWRzaS0+bGFuZXMgPSBkZXZpY2UtPmxhbmVzOwo+ICsJZHNpLT5sYW5lcyA9IGxh bmVzOwo+ICAJZHNpLT5jaGFubmVsID0gZGV2aWNlLT5jaGFubmVsOwo+ICAJZHNpLT5mb3JtYXQg PSBkZXZpY2UtPmZvcm1hdDsKPiAgCWRzaS0+bW9kZV9mbGFncyA9IGRldmljZS0+bW9kZV9mbGFn czsKPiArCj4gKwlpZiAoZHNpLT5zbGF2ZSkgewo+ICsJCWRzaS0+c2xhdmUtPmxhbmVzID0gbGFu ZXM7Cj4gKwkJZHNpLT5zbGF2ZS0+Y2hhbm5lbCA9IGRldmljZS0+Y2hhbm5lbDsKPiArCQlkc2kt PnNsYXZlLT5mb3JtYXQgPSBkZXZpY2UtPmZvcm1hdDsKPiArCQlkc2ktPnNsYXZlLT5tb2RlX2Zs YWdzID0gZGV2aWNlLT5tb2RlX2ZsYWdzOwo+ICsJfQo+ICsKPiAgCWRzaS0+cGFuZWwgPSBvZl9k cm1fZmluZF9wYW5lbChkZXZpY2UtPmRldi5vZl9ub2RlKTsKPiAgCWlmIChkc2ktPnBhbmVsKQo+ ICAJCXJldHVybiBkcm1fcGFuZWxfYXR0YWNoKGRzaS0+cGFuZWwsICZkc2ktPmNvbm5lY3Rvcik7 Cj4gQEAgLTc5MywxNSArODY3LDIyIEBAIHN0YXRpYyBzc2l6ZV90IGR3X21pcGlfZHNpX2hvc3Rf dHJhbnNmZXIoc3RydWN0IG1pcGlfZHNpX2hvc3QgKmhvc3QsCj4gIAlpbnQgcmV0Owo+ICAKPiAg CWR3X21pcGlfbWVzc2FnZV9jb25maWcoZHNpLCBtc2cpOwo+ICsJaWYgKGRzaS0+c2xhdmUpCj4g KwkJZHdfbWlwaV9tZXNzYWdlX2NvbmZpZyhkc2ktPnNsYXZlLCBtc2cpOwo+ICAKPiAgCXN3aXRj aCAobXNnLT50eXBlKSB7Cj4gIAljYXNlIE1JUElfRFNJX0RDU19TSE9SVF9XUklURToKPiAgCWNh c2UgTUlQSV9EU0lfRENTX1NIT1JUX1dSSVRFX1BBUkFNOgo+ICAJY2FzZSBNSVBJX0RTSV9TRVRf TUFYSU1VTV9SRVRVUk5fUEFDS0VUX1NJWkU6Cj4gKwljYXNlIE1JUElfRFNJX0dFTkVSSUNfU0hP UlRfV1JJVEVfMl9QQVJBTToKPiAgCQlyZXQgPSBkd19taXBpX2RzaV9kY3Nfc2hvcnRfd3JpdGUo ZHNpLCBtc2cpOwo+ICsJCWlmIChkc2ktPnNsYXZlKQo+ICsJCQlyZXQgPSBkd19taXBpX2RzaV9k Y3Nfc2hvcnRfd3JpdGUoZHNpLT5zbGF2ZSwgbXNnKTsKPiAgCQlicmVhazsKPiAgCWNhc2UgTUlQ SV9EU0lfRENTX0xPTkdfV1JJVEU6Cj4gIAkJcmV0ID0gZHdfbWlwaV9kc2lfZGNzX2xvbmdfd3Jp dGUoZHNpLCBtc2cpOwo+ICsJCWlmIChkc2ktPnNsYXZlKQo+ICsJCQlyZXQgPSBkd19taXBpX2Rz aV9kY3NfbG9uZ193cml0ZShkc2ktPnNsYXZlLCBtc2cpOwo+ICAJCWJyZWFrOwo+ICAJZGVmYXVs dDoKPiAgCQlkZXZfZXJyKGRzaS0+ZGV2LCAidW5zdXBwb3J0ZWQgbWVzc2FnZSB0eXBlIDB4JTAy eFxuIiwKPiBAQCAtODc1LDYgKzk1Niw1NSBAQCBzdGF0aWMgdm9pZCBkd19taXBpX2RzaV9pbml0 KHN0cnVjdCBkd19taXBpX2RzaSAqZHNpKQo+ICAJCSAgVFhfRVNDX0NMS19ESVZJRFNJT04oZXNj X2Nsa19kaXZpc2lvbikpOwo+ICB9Cj4gIAo+ICtzdGF0aWMgdm9pZCByb2NrY2hpcF9kc2lfZ3Jm X2NvbmZpZyhzdHJ1Y3QgZHdfbWlwaV9kc2kgKmRzaSwgaW50IHZvcF9pZCkKPiArewo+ICsJY29u c3Qgc3RydWN0IGR3X21pcGlfZHNpX3BsYXRfZGF0YSAqcGRhdGEgPSBkc2ktPnBkYXRhOwo+ICsJ aW50IHZhbCA9IDA7Cj4gKwlpbnQgcmV0Owo+ICsKPiArCS8qCj4gKwkgKiBGb3IgdGhlIFJLMzM5 OSwgdGhlIGNsayBvZiBncmYgbXVzdCBiZSBlbmFibGVkIGJlZm9yZSB3cml0aW5nIGdyZgo+ICsJ ICogcmVnaXN0ZXIuIEFuZCBmb3IgUkszMjg4IG9yIG90aGVyIHNvYywgdGhpcyBncmZfY2xrIG11 c3QgYmUgTlVMTCwKPiArCSAqIHRoZSBjbGtfcHJlcGFyZV9lbmFibGUgcmV0dXJuIHRydWUgZGly ZWN0bHkuCj4gKwkgKi8KPiArCXJldCA9IGNsa19wcmVwYXJlX2VuYWJsZShkc2ktPmdyZl9jbGsp Owo+ICsJaWYgKHJldCkgewo+ICsJCWRldl9lcnIoZHNpLT5kZXYsICJGYWlsZWQgdG8gZW5hYmxl IGdyZl9jbGs6ICVkXG4iLCByZXQpOwo+ICsJCXJldHVybjsKPiArCX0KPiArCj4gKwl2YWwgPSBw ZGF0YS0+ZHNpMF9lbl9iaXQgPDwgMTY7Cj4gKwlpZiAoZHNpLT5zbGF2ZSkKPiArCQl2YWwgfD0g cGRhdGEtPmRzaTFfZW5fYml0IDw8IDE2Owo+ICsJaWYgKHZvcF9pZCkgewo+ICsJCXZhbCB8PSBw ZGF0YS0+ZHNpMF9lbl9iaXQ7Cj4gKwkJaWYgKGRzaS0+c2xhdmUpCj4gKwkJCXZhbCB8PSBwZGF0 YS0+ZHNpMV9lbl9iaXQ7Cj4gKwl9Cj4gKwlyZWdtYXBfd3JpdGUoZHNpLT5ncmZfcmVnbWFwLCBw ZGF0YS0+Z3JmX3N3aXRjaF9yZWcsIHZhbCk7Cj4gKwo+ICsJaWYgKHBkYXRhLT5ncmZfZHNpMF9t b2RlX3JlZykKPiArCQlyZWdtYXBfd3JpdGUoZHNpLT5ncmZfcmVnbWFwLCBwZGF0YS0+Z3JmX2Rz aTBfbW9kZV9yZWcsCj4gKwkJCSAgICAgcGRhdGEtPmdyZl9kc2kwX21vZGUpOwo+ICsKPiArCWlm IChkc2ktPnNsYXZlKSB7Cj4gKwkJaWYgKHBkYXRhLT5ncmZfZHNpMV9tb2RlX3JlZzEpCj4gKwkJ CXJlZ21hcF93cml0ZShkc2ktPmdyZl9yZWdtYXAsIHBkYXRhLT5ncmZfZHNpMV9tb2RlX3JlZzEs Cj4gKwkJCQkgICAgIHBkYXRhLT5ncmZfZHNpMV9tb2RlKTsKPiArCQl2YWwgPSBwZGF0YS0+ZHNp MV9tYXN0ZXJzbGF2ZXogfAo+ICsJCSAgICAgIChwZGF0YS0+ZHNpMV9tYXN0ZXJzbGF2ZXogPDwg MTYpIHwKPiArCQkgICAgICAocGRhdGEtPmRzaTFfYmFzZWRpciA8PCAxNik7Cgp2YWwgaXMgb25s eSB1c2VkIGluIHRoZSBpZiBicmFuY2ggYmVsb3csIG5vIG5lZWQgdG8gY2FsY3VsYXRlIGl0IHdo ZW4KdGhlIGJyYW5jaCBpc24ndCBleGVjdXRlZC4KCj4gKwkJaWYgKHBkYXRhLT5ncmZfZHNpMV9t b2RlX3JlZzIpCj4gKwkJCXJlZ21hcF93cml0ZShkc2ktPmdyZl9yZWdtYXAsIHBkYXRhLT5ncmZf ZHNpMV9tb2RlX3JlZzIsCj4gKwkJCQkgICAgIHZhbCk7Cj4gKwkJaWYgKHBkYXRhLT5ncmZfZHNp MV9tb2RlX3JlZzEpCj4gKwkJCXJlZ21hcF93cml0ZShkc2ktPmdyZl9yZWdtYXAsIHBkYXRhLT5n cmZfZHNpMV9tb2RlX3JlZzEsCj4gKwkJCQkgICAgIHBkYXRhLT5ncmZfZHNpMV9lbmFibGUpOwo+ ICsJfQo+ICsKPiArCWNsa19kaXNhYmxlX3VucHJlcGFyZShkc2ktPmdyZl9jbGspOwo+ICt9Cj4g Kwo+ICBzdGF0aWMgdm9pZCBkd19taXBpX2RzaV9kcGlfY29uZmlnKHN0cnVjdCBkd19taXBpX2Rz aSAqZHNpLAo+ICAJCQkJICAgc3RydWN0IGRybV9kaXNwbGF5X21vZGUgKm1vZGUpCj4gIHsKPiBA QCAtOTE1LDcgKzEwNDUsMTQgQEAgc3RhdGljIHZvaWQgZHdfbWlwaV9kc2lfcGFja2V0X2hhbmRs ZXJfY29uZmlnKHN0cnVjdCBkd19taXBpX2RzaSAqZHNpKQo+ICBzdGF0aWMgdm9pZCBkd19taXBp X2RzaV92aWRlb19wYWNrZXRfY29uZmlnKHN0cnVjdCBkd19taXBpX2RzaSAqZHNpLAo+ICAJCQkJ CSAgICBzdHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAqbW9kZSkKPiAgewo+IC0JZHNpX3dyaXRlKGRz aSwgRFNJX1ZJRF9QS1RfU0laRSwgVklEX1BLVF9TSVpFKG1vZGUtPmhkaXNwbGF5KSk7Cj4gKwlp bnQgcGt0X3NpemU7Cj4gKwo+ICsJaWYgKGRzaS0+c2xhdmUgfHwgZHNpLT5tYXN0ZXIpCj4gKwkJ cGt0X3NpemUgPSBWSURfUEtUX1NJWkUobW9kZS0+aGRpc3BsYXkgLyAyKTsKPiArCWVsc2UKPiAr CQlwa3Rfc2l6ZSA9IFZJRF9QS1RfU0laRShtb2RlLT5oZGlzcGxheSk7Cj4gKwo+ICsJZHNpX3dy aXRlKGRzaSwgRFNJX1ZJRF9QS1RfU0laRSwgcGt0X3NpemUpOwo+ICB9Cj4gIAo+ICBzdGF0aWMg dm9pZCBkd19taXBpX2RzaV9jb21tYW5kX21vZGVfY29uZmlnKHN0cnVjdCBkd19taXBpX2RzaSAq ZHNpKQo+IEBAIC0xMDIwLDI0ICsxMTU3LDI2IEBAIHN0YXRpYyB2b2lkIGR3X21pcGlfZHNpX2Vu Y29kZXJfZGlzYWJsZShzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29kZXIpCj4gIAlkd19taXBpX2Rz aV9kaXNhYmxlKGRzaSk7Cj4gIAlwbV9ydW50aW1lX3B1dChkc2ktPmRldik7Cj4gIAljbGtfZGlz YWJsZV91bnByZXBhcmUoZHNpLT5wY2xrKTsKPiArCj4gKwlpZiAoZHNpLT5zbGF2ZSkgewo+ICsJ CWlmIChjbGtfcHJlcGFyZV9lbmFibGUoZHNpLT5zbGF2ZS0+cGNsaykpIHsKPiArCQkJZGV2X2Vy cihkc2ktPnNsYXZlLT5kZXYsICIlczogRmFpbGVkIHRvIGVuYWJsZSBwY2xrXG4iLCBfX2Z1bmNf Xyk7Cj4gKwkJCXJldHVybjsKPiArCQl9Cj4gKwkJZHdfbWlwaV9kc2lfZGlzYWJsZShkc2ktPnNs YXZlKTsKPiArCQlwbV9ydW50aW1lX3B1dChkc2ktPnNsYXZlLT5kZXYpOwo+ICsJCWNsa19kaXNh YmxlX3VucHJlcGFyZShkc2ktPnNsYXZlLT5wY2xrKTsKPiArCX0KPiArCj4gIAlkc2ktPmRwbXNf bW9kZSA9IERSTV9NT0RFX0RQTVNfT0ZGOwo+ICB9Cj4gIAo+IC1zdGF0aWMgdm9pZCBkd19taXBp X2RzaV9lbmNvZGVyX2VuYWJsZShzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29kZXIpCj4gK3N0YXRp YyB2b2lkIGR3X21pcGlfZHNpX2VuYWJsZShzdHJ1Y3QgZHdfbWlwaV9kc2kgKmRzaSwgc3RydWN0 IGRybV9kaXNwbGF5X21vZGUgKm1vZGUpCj4gIHsKPiAtCXN0cnVjdCBkd19taXBpX2RzaSAqZHNp ID0gZW5jb2Rlcl90b19kc2koZW5jb2Rlcik7Cj4gLQlzdHJ1Y3QgZHJtX2Rpc3BsYXlfbW9kZSAq bW9kZSA9ICZlbmNvZGVyLT5jcnRjLT5zdGF0ZS0+YWRqdXN0ZWRfbW9kZTsKPiAtCWNvbnN0IHN0 cnVjdCBkd19taXBpX2RzaV9wbGF0X2RhdGEgKnBkYXRhID0gZHNpLT5wZGF0YTsKPiAtCWludCBt dXggPSBkcm1fb2ZfZW5jb2Rlcl9hY3RpdmVfZW5kcG9pbnRfaWQoZHNpLT5kZXYtPm9mX25vZGUs IGVuY29kZXIpOwo+IC0JdTMyIHZhbDsKPiAtCWludCByZXQ7Cj4gLQo+IC0JcmV0ID0gZHdfbWlw aV9kc2lfZ2V0X2xhbmVfYnBzKGRzaSwgbW9kZSk7Cj4gLQlpZiAocmV0IDwgMCkKPiAtCQlyZXR1 cm47Cj4gLQo+IC0JaWYgKGRzaS0+ZHBtc19tb2RlID09IERSTV9NT0RFX0RQTVNfT04pCj4gKwlp ZiAoZHdfbWlwaV9kc2lfZ2V0X2xhbmVfYnBzKGRzaSwgbW9kZSkgPCAwKSB7Cj4gKwkJZGV2X2Vy cihkc2ktPmRldiwgIiVzOiBGYWlsZWQgdG8gZ2V0IGxhbmUgYnBzXG4iLCBfX2Z1bmNfXyk7Cj4g IAkJcmV0dXJuOwo+ICsJfQo+ICAKPiAgCWlmIChjbGtfcHJlcGFyZV9lbmFibGUoZHNpLT5wY2xr KSkgewo+ICAJCWRldl9lcnIoZHNpLT5kZXYsICIlczogRmFpbGVkIHRvIGVuYWJsZSBwY2xrXG4i LCBfX2Z1bmNfXyk7Cj4gQEAgLTEwNTcsNDMgKzExOTYsNDIgQEAgc3RhdGljIHZvaWQgZHdfbWlw aV9kc2lfZW5jb2Rlcl9lbmFibGUoc3RydWN0IGRybV9lbmNvZGVyICplbmNvZGVyKQo+ICAJZHdf bWlwaV9kc2lfZHBoeV9pbnRlcmZhY2VfY29uZmlnKGRzaSk7Cj4gIAlkd19taXBpX2RzaV9jbGVh cl9lcnIoZHNpKTsKPiAgCj4gLQkvKgo+IC0JICogRm9yIHRoZSBSSzMzOTksIHRoZSBjbGsgb2Yg Z3JmIG11c3QgYmUgZW5hYmxlZCBiZWZvcmUgd3JpdGluZyBncmYKPiAtCSAqIHJlZ2lzdGVyLiBB bmQgZm9yIFJLMzI4OCBvciBvdGhlciBzb2MsIHRoaXMgZ3JmX2NsayBtdXN0IGJlIE5VTEwsCj4g LQkgKiB0aGUgY2xrX3ByZXBhcmVfZW5hYmxlIHJldHVybiB0cnVlIGRpcmVjdGx5Lgo+IC0JICov Cj4gLQlyZXQgPSBjbGtfcHJlcGFyZV9lbmFibGUoZHNpLT5ncmZfY2xrKTsKPiAtCWlmIChyZXQp IHsKPiAtCQlkZXZfZXJyKGRzaS0+ZGV2LCAiRmFpbGVkIHRvIGVuYWJsZSBncmZfY2xrOiAlZFxu IiwgcmV0KTsKPiAtCQlyZXR1cm47Cj4gLQl9Cj4gLQo+IC0JaWYgKHBkYXRhLT5ncmZfZHNpMF9t b2RlX3JlZykKPiAtCQlyZWdtYXBfd3JpdGUoZHNpLT5ncmZfcmVnbWFwLCBwZGF0YS0+Z3JmX2Rz aTBfbW9kZV9yZWcsCj4gLQkJCSAgICAgcGRhdGEtPmdyZl9kc2kwX21vZGUpOwo+IC0KPiAgCWR3 X21pcGlfZHNpX3BoeV9pbml0KGRzaSk7Cj4gIAlkd19taXBpX2RzaV93YWl0X2Zvcl90d29fZnJh bWVzKG1vZGUpOwo+ICAKPiAgCWR3X21pcGlfZHNpX3NldF9tb2RlKGRzaSwgRFdfTUlQSV9EU0lf Q01EX01PREUpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBkd19taXBpX2RzaV9lbmNvZGVyX2Vu YWJsZShzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29kZXIpCj4gK3sKPiArCXN0cnVjdCBkd19taXBp X2RzaSAqZHNpID0gZW5jb2Rlcl90b19kc2koZW5jb2Rlcik7Cj4gKwlzdHJ1Y3QgZHJtX2Rpc3Bs YXlfbW9kZSAqbW9kZSA9ICZlbmNvZGVyLT5jcnRjLT5zdGF0ZS0+YWRqdXN0ZWRfbW9kZTsKPiAr CWludCBtdXggPSBkcm1fb2ZfZW5jb2Rlcl9hY3RpdmVfZW5kcG9pbnRfaWQoZHNpLT5kZXYtPm9m X25vZGUsIGVuY29kZXIpOwo+ICsKPiArCWlmIChkc2ktPmRwbXNfbW9kZSA9PSBEUk1fTU9ERV9E UE1TX09OKQo+ICsJCXJldHVybjsKPiArCj4gKwlyb2NrY2hpcF9kc2lfZ3JmX2NvbmZpZyhkc2ks IG11eCk7Cj4gKwlkZXZfZGJnKGRzaS0+ZGV2LCAidm9wICVzIG91dHB1dCB0byBkc2kwXG4iLCAo bXV4KSA/ICJMSVQiIDogIkJJRyIpOwo+ICsKPiArCWR3X21pcGlfZHNpX2VuYWJsZShkc2ksIG1v ZGUpOwo+ICsJaWYgKGRzaS0+c2xhdmUpCj4gKwkJZHdfbWlwaV9kc2lfZW5hYmxlKGRzaS0+c2xh dmUsIG1vZGUpOwo+ICsKPiAgCWlmIChkcm1fcGFuZWxfcHJlcGFyZShkc2ktPnBhbmVsKSkKPiAg CQlkZXZfZXJyKGRzaS0+ZGV2LCAiZmFpbGVkIHRvIHByZXBhcmUgcGFuZWxcbiIpOwo+ICAKPiAg CWR3X21pcGlfZHNpX3NldF9tb2RlKGRzaSwgRFdfTUlQSV9EU0lfVklEX01PREUpOwo+ICsJaWYg KGRzaS0+c2xhdmUpCj4gKwkJZHdfbWlwaV9kc2lfc2V0X21vZGUoZHNpLT5zbGF2ZSwgRFdfTUlQ SV9EU0lfVklEX01PREUpOwo+ICsKPiAgCWRybV9wYW5lbF9lbmFibGUoZHNpLT5wYW5lbCk7Cj4g IAo+ICAJY2xrX2Rpc2FibGVfdW5wcmVwYXJlKGRzaS0+cGNsayk7Cj4gKwlpZiAoZHNpLT5zbGF2 ZSkKPiArCQljbGtfZGlzYWJsZV91bnByZXBhcmUoZHNpLT5zbGF2ZS0+cGNsayk7Cj4gIAo+IC0J aWYgKG11eCkKPiAtCQl2YWwgPSBwZGF0YS0+ZHNpMF9lbl9iaXQgfCAocGRhdGEtPmRzaTBfZW5f Yml0IDw8IDE2KTsKPiAtCWVsc2UKPiAtCQl2YWwgPSBwZGF0YS0+ZHNpMF9lbl9iaXQgPDwgMTY7 Cj4gLQo+IC0JcmVnbWFwX3dyaXRlKGRzaS0+Z3JmX3JlZ21hcCwgcGRhdGEtPmdyZl9zd2l0Y2hf cmVnLCB2YWwpOwo+IC0JZGV2X2RiZyhkc2ktPmRldiwgInZvcCAlcyBvdXRwdXQgdG8gZHNpMFxu IiwgKG11eCkgPyAiTElUIiA6ICJCSUciKTsKPiAgCWRzaS0+ZHBtc19tb2RlID0gRFJNX01PREVf RFBNU19PTjsKPiAtCj4gLQljbGtfZGlzYWJsZV91bnByZXBhcmUoZHNpLT5ncmZfY2xrKTsKPiAg fQo+ICAKPiAgc3RhdGljIGludAo+IEBAIC0xMTIxLDYgKzEyNTksOSBAQCBzdGF0aWMgdm9pZCBk d19taXBpX2RzaV9lbmNvZGVyX2VuYWJsZShzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29kZXIpCj4g IAo+ICAJcy0+b3V0cHV0X3R5cGUgPSBEUk1fTU9ERV9DT05ORUNUT1JfRFNJOwo+ICAKPiArCWlm IChkc2ktPnNsYXZlKQo+ICsJCXMtPm91dHB1dF9mbGFncyA9IFJPQ0tDSElQX09VVFBVVF9EU0lf RFVBTF9DSEFOTkVMOwo+ICsKPiAgCXJldHVybiAwOwo+ICB9Cj4gIAo+IEBAIC0xMjI2LDYgKzEz NjcsMTMgQEAgc3RhdGljIGludCByb2NrY2hpcF9taXBpX3BhcnNlX2R0KHN0cnVjdCBkd19taXBp X2RzaSAqZHNpKQo+ICAJLmdyZl9zd2l0Y2hfcmVnID0gUkszMzk5X0dSRl9TT0NfQ09OMjAsCj4g IAkuZ3JmX2RzaTBfbW9kZSA9IFJLMzM5OV9HUkZfRFNJX01PREUsCj4gIAkuZ3JmX2RzaTBfbW9k ZV9yZWcgPSBSSzMzOTlfR1JGX1NPQ19DT04yMiwKPiArCS5ncmZfZHNpMV9tb2RlID0gUkszMzk5 X0dSRl9EU0kxX01PREUsCj4gKwkuZ3JmX2RzaTFfZW5hYmxlID0gUkszMzk5X0dSRl9EU0kxX0VO QUJMRSwKPiArCS5ncmZfZHNpMV9tb2RlX3JlZzEgPSBSSzMzOTlfR1JGX1NPQ19DT04yMywKPiAr CS5kc2kxX2Jhc2VkaXIgPSBSSzMzOTlfVFhSWF9CQVNFRElSLAo+ICsJLmRzaTFfbWFzdGVyc2xh dmV6ID0gUkszMzk5X1RYUlhfTUFTVEVSU0xBVkVaLAo+ICsJLmRzaTFfZW5hYmxlY2xrID0gUksz Mzk5X1RYUlhfRU5BQkxFQ0xLLAo+ICsJLmdyZl9kc2kxX21vZGVfcmVnMiA9IFJLMzM5OV9HUkZf U09DX0NPTjI0LAo+ICAJLmZsYWdzID0gRFdfTUlQSV9ORUVEU19QSFlfQ0ZHX0NMSyB8IERXX01J UElfTkVFRFNfR1JGX0NMSywKPiAgCS5tYXhfZGF0YV9sYW5lcyA9IDQsCj4gIH07Cj4gQEAgLTEy NDIsMTcgKzEzOTAsMTA3IEBAIHN0YXRpYyBpbnQgcm9ja2NoaXBfbWlwaV9wYXJzZV9kdChzdHJ1 Y3QgZHdfbWlwaV9kc2kgKmRzaSkKPiAgfTsKPiAgTU9EVUxFX0RFVklDRV9UQUJMRShvZiwgZHdf bWlwaV9kc2lfZHRfaWRzKTsKPiAgCj4gKwo+ICtzdGF0aWMgaW50IHJvY2tjaGlwX2RzaV9kdWFs X2NoYW5uZWxfcHJvYmUoc3RydWN0IGR3X21pcGlfZHNpICpkc2kpCj4gK3sKPiArCXN0cnVjdCBk ZXZpY2Vfbm9kZSAqbnA7Cj4gKwlzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpzZWNvbmRhcnk7Cj4g Kwo+ICsJbnAgPSBvZl9wYXJzZV9waGFuZGxlKGRzaS0+ZGV2LT5vZl9ub2RlLCAicm9ja2NoaXAs ZHVhbC1jaGFubmVsIiwgMCk7Cj4gKwlpZiAobnApIHsKPiArCQlzZWNvbmRhcnkgPSBvZl9maW5k X2RldmljZV9ieV9ub2RlKG5wKTsKPiArCQlkc2ktPnNsYXZlID0gcGxhdGZvcm1fZ2V0X2RydmRh dGEoc2Vjb25kYXJ5KTsKPiArCQlvZl9ub2RlX3B1dChucCk7Cj4gKwo+ICsJCWlmICghZHNpLT5z bGF2ZSkKPiArCQkJcmV0dXJuIC1FUFJPQkVfREVGRVI7Cj4gKwo+ICsJCWRzaS0+c2xhdmUtPm1h c3RlciA9IGRzaTsKPiArCX0KPiArCj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiAgc3RhdGljIGlu dCBkd19taXBpX2RzaV9iaW5kKHN0cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0IGRldmljZSAqbWFz dGVyLAo+ICAJCQkgICAgdm9pZCAqZGF0YSkKPiAgewo+ICsJc3RydWN0IGRybV9kZXZpY2UgKmRy bSA9IGRhdGE7Cj4gKwlzdHJ1Y3QgZHdfbWlwaV9kc2kgKmRzaSA9IGRldl9nZXRfZHJ2ZGF0YShk ZXYpOwo+ICsJaW50IHJldDsKPiArCj4gKwlyZXQgPSByb2NrY2hpcF9kc2lfZHVhbF9jaGFubmVs X3Byb2JlKGRzaSk7Cj4gKwlpZiAocmV0KQo+ICsJCXJldHVybiByZXQ7Cj4gKwo+ICsJcmV0ID0g Y2xrX3ByZXBhcmVfZW5hYmxlKGRzaS0+cGxscmVmX2Nsayk7Cj4gKwlpZiAocmV0KSB7Cj4gKwkJ ZGV2X2VycihkZXYsICIlczogRmFpbGVkIHRvIGVuYWJsZSBwbGxyZWZfY2xrXG4iLCBfX2Z1bmNf Xyk7Cj4gKwkJcmV0dXJuIHJldDsKPiArCX0KPiArCj4gKwlwbV9ydW50aW1lX2VuYWJsZShkZXYp Owo+ICsKPiArCWlmIChkc2ktPm1hc3RlcikKPiArCQlyZXR1cm4gMDsKPiArCj4gKwlyZXQgPSBk d19taXBpX2RzaV9yZWdpc3Rlcihkcm0sIGRzaSk7Cj4gKwlpZiAocmV0KSB7Cj4gKwkJZGV2X2Vy cihkZXYsICJGYWlsZWQgdG8gcmVnaXN0ZXIgbWlwaV9kc2k6ICVkXG4iLCByZXQpOwo+ICsJCWdv dG8gZXJyX3BsbHJlZjsKPiArCX0KPiArCj4gKwlkc2ktPmRzaV9ob3N0Lm9wcyA9ICZkd19taXBp X2RzaV9ob3N0X29wczsKPiArCWRzaS0+ZHNpX2hvc3QuZGV2ID0gZGV2Owo+ICsJcmV0ID0gbWlw aV9kc2lfaG9zdF9yZWdpc3RlcigmZHNpLT5kc2lfaG9zdCk7Cj4gKwlpZiAocmV0KSB7Cj4gKwkJ ZGV2X2VycihkZXYsICJGYWlsZWQgdG8gcmVnaXN0ZXIgTUlQSSBob3N0OiAlZFxuIiwgcmV0KTsK PiArCQlnb3RvIGVycl9jbGVhbnVwOwo+ICsJfQo+ICsKPiArCWlmICghZHNpLT5wYW5lbCkgewo+ ICsJCXJldCA9IC1FUFJPQkVfREVGRVI7Cj4gKwkJZ290byBlcnJfbWlwaV9kc2lfaG9zdDsKPiAr CX0KPiArCj4gKwlyZXR1cm4gMDsKPiArCj4gK2Vycl9taXBpX2RzaV9ob3N0Ogo+ICsJbWlwaV9k c2lfaG9zdF91bnJlZ2lzdGVyKCZkc2ktPmRzaV9ob3N0KTsKPiArZXJyX2NsZWFudXA6Cj4gKwlk cm1fZW5jb2Rlcl9jbGVhbnVwKCZkc2ktPmVuY29kZXIpOwo+ICsJZHJtX2Nvbm5lY3Rvcl9jbGVh bnVwKCZkc2ktPmNvbm5lY3Rvcik7Cj4gK2Vycl9wbGxyZWY6Cj4gKwlwbV9ydW50aW1lX2Rpc2Fi bGUoZGV2KTsKPiArCWNsa19kaXNhYmxlX3VucHJlcGFyZShkc2ktPnBsbHJlZl9jbGspOwo+ICsJ cmV0dXJuIHJldDsKPiArfQo+ICsKPiArc3RhdGljIHZvaWQgZHdfbWlwaV9kc2lfdW5iaW5kKHN0 cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0IGRldmljZSAqbWFzdGVyLAo+ICsJCQkgICAgICAgdm9p ZCAqZGF0YSkKPiArewo+ICsJc3RydWN0IGR3X21pcGlfZHNpICpkc2kgPSBkZXZfZ2V0X2RydmRh dGEoZGV2KTsKPiArCj4gKwltaXBpX2RzaV9ob3N0X3VucmVnaXN0ZXIoJmRzaS0+ZHNpX2hvc3Qp Owo+ICsJcG1fcnVudGltZV9kaXNhYmxlKGRldik7Cj4gKwlpZiAoZHNpLT5zbGF2ZSkKPiArCQlw bV9ydW50aW1lX2Rpc2FibGUoZHNpLT5zbGF2ZS0+ZGV2KTsKPiArCWNsa19kaXNhYmxlX3VucHJl cGFyZShkc2ktPnBsbHJlZl9jbGspOwo+ICt9Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IGNv bXBvbmVudF9vcHMgZHdfbWlwaV9kc2lfb3BzID0gewo+ICsJLmJpbmQJPSBkd19taXBpX2RzaV9i aW5kLAo+ICsJLnVuYmluZAk9IGR3X21pcGlfZHNpX3VuYmluZCwKPiArfTsKPiArCj4gK3N0YXRp YyBpbnQgZHdfbWlwaV9kc2lfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiAr ewo+ICsJc3RydWN0IGRldmljZSAqZGV2ID0gJnBkZXYtPmRldjsKPiAgCWNvbnN0IHN0cnVjdCBv Zl9kZXZpY2VfaWQgKm9mX2lkID0KPiAgCQkJb2ZfbWF0Y2hfZGV2aWNlKGR3X21pcGlfZHNpX2R0 X2lkcywgZGV2KTsKPiAgCWNvbnN0IHN0cnVjdCBkd19taXBpX2RzaV9wbGF0X2RhdGEgKnBkYXRh ID0gb2ZfaWQtPmRhdGE7Cj4gLQlzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2ID0gdG9fcGxh dGZvcm1fZGV2aWNlKGRldik7Cj4gLQlzdHJ1Y3QgcmVzZXRfY29udHJvbCAqYXBiX3JzdDsKPiAt CXN0cnVjdCBkcm1fZGV2aWNlICpkcm0gPSBkYXRhOwo+ICAJc3RydWN0IGR3X21pcGlfZHNpICpk c2k7Cj4gIAlzdHJ1Y3QgcmVzb3VyY2UgKnJlczsKPiArCXN0cnVjdCByZXNldF9jb250cm9sICph cGJfcnN0Owo+ICAJaW50IHJldDsKPiAgCj4gIAlkc2kgPSBkZXZtX2t6YWxsb2MoZGV2LCBzaXpl b2YoKmRzaSksIEdGUF9LRVJORUwpOwo+IEBAIC0xMjYyLDYgKzE1MDAsNyBAQCBzdGF0aWMgaW50 IGR3X21pcGlfZHNpX2JpbmQoc3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3QgZGV2aWNlICptYXN0 ZXIsCj4gIAlkc2ktPmRldiA9IGRldjsKPiAgCWRzaS0+cGRhdGEgPSBwZGF0YTsKPiAgCWRzaS0+ ZHBtc19tb2RlID0gRFJNX01PREVfRFBNU19PRkY7Cj4gKwlkZXZfc2V0X2RydmRhdGEoZGV2LCBk c2kpOwo+ICAKPiAgCXJldCA9IHJvY2tjaGlwX21pcGlfcGFyc2VfZHQoZHNpKTsKPiAgCWlmIChy ZXQpCj4gQEAgLTEzMzYsNjMgKzE1NzUsNiBAQCBzdGF0aWMgaW50IGR3X21pcGlfZHNpX2JpbmQo c3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3QgZGV2aWNlICptYXN0ZXIsCj4gIAkJfQo+ICAJfQo+ ICAKPiAtCXJldCA9IGNsa19wcmVwYXJlX2VuYWJsZShkc2ktPnBsbHJlZl9jbGspOwo+IC0JaWYg KHJldCkgewo+IC0JCWRldl9lcnIoZGV2LCAiJXM6IEZhaWxlZCB0byBlbmFibGUgcGxscmVmX2Ns a1xuIiwgX19mdW5jX18pOwo+IC0JCXJldHVybiByZXQ7Cj4gLQl9Cj4gLQo+IC0JcmV0ID0gZHdf bWlwaV9kc2lfcmVnaXN0ZXIoZHJtLCBkc2kpOwo+IC0JaWYgKHJldCkgewo+IC0JCWRldl9lcnIo ZGV2LCAiRmFpbGVkIHRvIHJlZ2lzdGVyIG1pcGlfZHNpOiAlZFxuIiwgcmV0KTsKPiAtCQlnb3Rv IGVycl9wbGxyZWY7Cj4gLQl9Cj4gLQo+IC0JcG1fcnVudGltZV9lbmFibGUoZGV2KTsKPiAtCj4g LQlkc2ktPmRzaV9ob3N0Lm9wcyA9ICZkd19taXBpX2RzaV9ob3N0X29wczsKPiAtCWRzaS0+ZHNp X2hvc3QuZGV2ID0gZGV2Owo+IC0JcmV0ID0gbWlwaV9kc2lfaG9zdF9yZWdpc3RlcigmZHNpLT5k c2lfaG9zdCk7Cj4gLQlpZiAocmV0KSB7Cj4gLQkJZGV2X2VycihkZXYsICJGYWlsZWQgdG8gcmVn aXN0ZXIgTUlQSSBob3N0OiAlZFxuIiwgcmV0KTsKPiAtCQlnb3RvIGVycl9jbGVhbnVwOwo+IC0J fQo+IC0KPiAtCWlmICghZHNpLT5wYW5lbCkgewo+IC0JCXJldCA9IC1FUFJPQkVfREVGRVI7Cj4g LQkJZ290byBlcnJfbWlwaV9kc2lfaG9zdDsKPiAtCX0KPiAtCj4gLQlkZXZfc2V0X2RydmRhdGEo ZGV2LCBkc2kpOwo+IC0JcmV0dXJuIDA7Cj4gLQo+IC1lcnJfbWlwaV9kc2lfaG9zdDoKPiAtCW1p cGlfZHNpX2hvc3RfdW5yZWdpc3RlcigmZHNpLT5kc2lfaG9zdCk7Cj4gLWVycl9jbGVhbnVwOgo+ IC0JZHJtX2VuY29kZXJfY2xlYW51cCgmZHNpLT5lbmNvZGVyKTsKPiAtCWRybV9jb25uZWN0b3Jf Y2xlYW51cCgmZHNpLT5jb25uZWN0b3IpOwo+IC1lcnJfcGxscmVmOgo+IC0JY2xrX2Rpc2FibGVf dW5wcmVwYXJlKGRzaS0+cGxscmVmX2Nsayk7Cj4gLQlyZXR1cm4gcmV0Owo+IC19Cj4gLQo+IC1z dGF0aWMgdm9pZCBkd19taXBpX2RzaV91bmJpbmQoc3RydWN0IGRldmljZSAqZGV2LCBzdHJ1Y3Qg ZGV2aWNlICptYXN0ZXIsCj4gLQkJCSAgICAgICB2b2lkICpkYXRhKQo+IC17Cj4gLQlzdHJ1Y3Qg ZHdfbWlwaV9kc2kgKmRzaSA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOwo+IC0KPiAtCW1pcGlfZHNp X2hvc3RfdW5yZWdpc3RlcigmZHNpLT5kc2lfaG9zdCk7Cj4gLQlwbV9ydW50aW1lX2Rpc2FibGUo ZGV2KTsKPiAtCWNsa19kaXNhYmxlX3VucHJlcGFyZShkc2ktPnBsbHJlZl9jbGspOwo+IC19Cj4g LQo+IC1zdGF0aWMgY29uc3Qgc3RydWN0IGNvbXBvbmVudF9vcHMgZHdfbWlwaV9kc2lfb3BzID0g ewo+IC0JLmJpbmQJPSBkd19taXBpX2RzaV9iaW5kLAo+IC0JLnVuYmluZAk9IGR3X21pcGlfZHNp X3VuYmluZCwKPiAtfTsKPiAtCj4gLXN0YXRpYyBpbnQgZHdfbWlwaV9kc2lfcHJvYmUoc3RydWN0 IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiAtewo+ICAJcmV0dXJuIGNvbXBvbmVudF9hZGQoJnBk ZXYtPmRldiwgJmR3X21pcGlfZHNpX29wcyk7Cj4gIH0KPiAgCj4gZGlmZiAtLWdpdCBhL2RyaXZl cnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hpcF9kcm1fZHJ2LmggYi9kcml2ZXJzL2dwdS9kcm0v cm9ja2NoaXAvcm9ja2NoaXBfZHJtX2Rydi5oCj4gaW5kZXggYzdlOTZiOC4uNTFhZDFjMiAxMDA2 NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfZHJtX2Rydi5oCj4g KysrIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX2RybV9kcnYuaAo+IEBAIC0z Niw2ICszNiw3IEBAIHN0cnVjdCByb2NrY2hpcF9jcnRjX3N0YXRlIHsKPiAgCXN0cnVjdCBkcm1f Y3J0Y19zdGF0ZSBiYXNlOwo+ICAJaW50IG91dHB1dF90eXBlOwo+ICAJaW50IG91dHB1dF9tb2Rl Owo+ICsJaW50IG91dHB1dF9mbGFnczsKPiAgfTsKPiAgI2RlZmluZSB0b19yb2NrY2hpcF9jcnRj X3N0YXRlKHMpIFwKPiAgCQljb250YWluZXJfb2Yocywgc3RydWN0IHJvY2tjaGlwX2NydGNfc3Rh dGUsIGJhc2UpCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hp cF9kcm1fdm9wLmMgYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfZHJtX3ZvcC5j Cj4gaW5kZXggYmY5ZWQwZS4uY2I0MGNkZCAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0v cm9ja2NoaXAvcm9ja2NoaXBfZHJtX3ZvcC5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tj aGlwL3JvY2tjaGlwX2RybV92b3AuYwo+IEBAIC05MTcsNiArOTE3LDggQEAgc3RhdGljIHZvaWQg dm9wX2NydGNfYXRvbWljX2VuYWJsZShzdHJ1Y3QgZHJtX2NydGMgKmNydGMsCj4gIAljYXNlIERS TV9NT0RFX0NPTk5FQ1RPUl9EU0k6Cj4gIAkJVk9QX1JFR19TRVQodm9wLCBvdXRwdXQsIG1pcGlf cGluX3BvbCwgcGluX3BvbCk7Cj4gIAkJVk9QX1JFR19TRVQodm9wLCBvdXRwdXQsIG1pcGlfZW4s IDEpOwo+ICsJCVZPUF9SRUdfU0VUKHZvcCwgb3V0cHV0LCBtaXBpX2R1YWxfY2hhbm5lbF9lbiwK PiArCQkJISEocy0+b3V0cHV0X2ZsYWdzICYgUk9DS0NISVBfT1VUUFVUX0RTSV9EVUFMX0NIQU5O RUwpKTsKPiAgCQlicmVhazsKPiAgCWNhc2UgRFJNX01PREVfQ09OTkVDVE9SX0Rpc3BsYXlQb3J0 Ogo+ICAJCXBpbl9wb2wgJj0gfkJJVChEQ0xLX0lOVkVSVCk7Cj4gZGlmZiAtLWdpdCBhL2RyaXZl cnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hpcF9kcm1fdm9wLmggYi9kcml2ZXJzL2dwdS9kcm0v cm9ja2NoaXAvcm9ja2NoaXBfZHJtX3ZvcC5oCj4gaW5kZXggNTZiYmQyZS4uZDE4NDUzMSAxMDA2 NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfZHJtX3ZvcC5oCj4g KysrIGIvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX2RybV92b3AuaAo+IEBAIC02 MCw2ICs2MCw3IEBAIHN0cnVjdCB2b3Bfb3V0cHV0IHsKPiAgCXN0cnVjdCB2b3BfcmVnIGVkcF9l bjsKPiAgCXN0cnVjdCB2b3BfcmVnIGhkbWlfZW47Cj4gIAlzdHJ1Y3Qgdm9wX3JlZyBtaXBpX2Vu Owo+ICsJc3RydWN0IHZvcF9yZWcgbWlwaV9kdWFsX2NoYW5uZWxfZW47Cj4gIAlzdHJ1Y3Qgdm9w X3JlZyByZ2JfZW47Cj4gIH07Cj4gIAo+IEBAIC0yMTIsNiArMjEzLDggQEAgc3RydWN0IHZvcF9k YXRhIHsKPiAgLyogZm9yIHVzZSBzcGVjaWFsIG91dGZhY2UgKi8KPiAgI2RlZmluZSBST0NLQ0hJ UF9PVVRfTU9ERV9BQUFBCTE1Cj4gIAo+ICsjZGVmaW5lIFJPQ0tDSElQX09VVFBVVF9EU0lfRFVB TF9DSEFOTkVMCUJJVCgwKQo+ICsKPiAgZW51bSBhbHBoYV9tb2RlIHsKPiAgCUFMUEhBX1NUUkFJ R0hULAo+ICAJQUxQSEFfSU5WRVJTRSwKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJl ZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGlu Zm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1033001AbdI0BZR (ORCPT ); Tue, 26 Sep 2017 21:25:17 -0400 Received: from mail-pf0-f173.google.com ([209.85.192.173]:56843 "EHLO mail-pf0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1032894AbdI0BZK (ORCPT ); Tue, 26 Sep 2017 21:25:10 -0400 X-Google-Smtp-Source: AOwi7QAeeBiU7tIkQdgw5jiRTv3K8qiGalmUWYRcQpwR+xxdcqVmPNNGkh7uCiVdTNHkBTQqmxacXg== Date: Tue, 26 Sep 2017 18:25:07 -0700 From: Matthias Kaehlcke To: Nickey Yang Cc: mark.yao@rock-chips.com, robh+dt@kernel.org, heiko@sntech.de, mark.rutland@arm.com, airlied@linux.ie, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, seanpaul@chromium.org, briannorris@chromium.org, hl@rock-chips.com, zyw@rock-chips.com, bivvy.bi@rock-chips.com, xbl@rock-chips.com Subject: Re: [PATCH v2 2/8] drm/rockchip/dsi: add dual mipi channel support Message-ID: <20170927012507.GK173745@google.com> References: <1506412523-1766-1-git-send-email-nickey.yang@rock-chips.com> <1506412523-1766-2-git-send-email-nickey.yang@rock-chips.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1506412523-1766-2-git-send-email-nickey.yang@rock-chips.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Nickey, please see my comment inline. (Note: I'm no export on MIPI DSI in general or this driver/controller in particular, my reviews of this driver are more focussed on C and generic kernel stuff, than on the details of the interaction with the controller) El Tue, Sep 26, 2017 at 03:55:17PM +0800 Nickey Yang ha dit: > This patch add dual mipi channel support: > 1.add definition of dsi1 register and grf operation. > 2.dsi0 and dsi1 will work in master and slave mode > when driving dual mipi panel. > > Signed-off-by: Nickey Yang > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 390 ++++++++++++++++++++-------- > drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 + > drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 + > drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 3 + > 4 files changed, 292 insertions(+), 104 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index c933a3a..191037c 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -39,8 +39,58 @@ > #define RK3399_DSI1_SEL_VOP_LIT BIT(4) > > /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */ > -#define RK3399_GRF_SOC_CON22 0x6258 > -#define RK3399_GRF_DSI_MODE 0xffff0000 > +#define RK3399_GRF_SOC_CON22 0x6258 > +#define DPHY_TX0_TURNREQUEST_SET ((0xf << 12) << 16) > +#define DPHY_TX0_TURNREQUEST_DISABLE (0x0 << 12) > +#define DPHY_TX0_TURNREQUEST_ENABLE (0xf << 12) > +#define DPHY_TX0_TURNDISABLE_SET ((0xf << 8) << 16) > +#define DPHY_TX0_TURNDISABLE_DISABLE (0x0 << 8) > +#define DPHY_TX0_TURNDISABLE_ENABLE (0xf << 8) > +#define DPHY_TX0_FORCETXSTOPMODE_SET ((0xf << 4) << 16) > +#define DPHY_TX0_FORCETXSTOPMODE_DISABLE (0x0 << 4) > +#define DPHY_TX0_FORCETXSTOPMODE_ENABLE (0xf << 4) > +#define DPHY_TX0_FORCETRXMODE_SET ((0xf << 0) << 16) > +#define DPHY_TX0_FORCETRXMODE_DISABLE 0x0 > +#define DPHY_TX0_FORCETRXMODE_ENABLE 0xf > +#define RK3399_GRF_DSI_MODE ((DPHY_TX0_TURNREQUEST_SET | \ > + DPHY_TX0_TURNDISABLE_SET | \ > + DPHY_TX0_FORCETXSTOPMODE_SET | \ > + DPHY_TX0_FORCETRXMODE_SET) | \ > + (DPHY_TX0_TURNREQUEST_DISABLE | \ > + DPHY_TX0_TURNDISABLE_DISABLE | \ > + DPHY_TX0_FORCETXSTOPMODE_DISABLE | \ > + DPHY_TX0_FORCETRXMODE_DISABLE)) > + > + > +/* disable turndisable, forcetxstopmode, forcerxmode, enable */ > +#define RK3399_GRF_SOC_CON23 0x625c > +#define DPHY_TX1RX1_TURNDISABLE_SET ((0xf << 12) << 16) > +#define DPHY_TX1RX1_TURNDISABLE_DISABLE (0x0 << 12) > +#define DPHY_TX1RX1_TURNDISABLE_ENABLE (0xf << 12) > +#define DPHY_TX1RX1_FORCETXSTOPMODE_SET ((0xf << 8) << 16) > +#define DPHY_TX1RX1_FORCETXSTOPMODE_DISABLE (0x0 << 8) > +#define DPHY_TX1RX1_FORCETXSTOPMODE_ENABLE (0xf << 8) > +#define DPHY_TX1RX1_FORCERXMODE_SET ((0xf << 4) << 16) > +#define DPHY_TX1RX1_FORCERXMODE_DISABLE (0x0 << 4) > +#define DPHY_TX1RX1_FORCERXMODE_ENABLE (0xf << 4) > +#define DPHY_TX1RX1_ENABLE_SET ((0xf << 0) << 16) > +#define DPHY_TX1RX1_ENABLE_DISABLE 0x0 > +#define DPHY_TX1RX1_ENABLE_ENABLE 0xf > +#define RK3399_GRF_DSI1_MODE ((DPHY_TX1RX1_TURNDISABLE_SET | \ > + DPHY_TX1RX1_FORCETXSTOPMODE_SET | \ > + DPHY_TX1RX1_FORCERXMODE_SET | \ > + DPHY_TX1RX1_ENABLE_SET) | \ > + (DPHY_TX0_TURNREQUEST_DISABLE | \ > + DPHY_TX0_TURNDISABLE_DISABLE | \ > + DPHY_TX0_FORCETXSTOPMODE_DISABLE | \ > + DPHY_TX0_FORCETRXMODE_DISABLE)) > +#define RK3399_GRF_DSI1_ENABLE ((DPHY_TX1RX1_ENABLE_SET | \ > + DPHY_TX1RX1_ENABLE_ENABLE)) > + > +#define RK3399_GRF_SOC_CON24 0x6260 > +#define RK3399_TXRX_MASTERSLAVEZ BIT(7) > +#define RK3399_TXRX_ENABLECLK BIT(6) > +#define RK3399_TXRX_BASEDIR BIT(5) > > #define DSI_VERSION 0x00 > #define DSI_PWR_UP 0x04 > @@ -304,6 +354,13 @@ struct dw_mipi_dsi_plat_data { > u32 grf_switch_reg; > u32 grf_dsi0_mode; > u32 grf_dsi0_mode_reg; > + u32 grf_dsi1_mode; > + u32 grf_dsi1_enable; > + u32 grf_dsi1_mode_reg1; > + u32 dsi1_basedir; > + u32 dsi1_masterslavez; > + u32 dsi1_enableclk; > + u32 grf_dsi1_mode_reg2; > unsigned int flags; > unsigned int max_data_lanes; > }; > @@ -322,6 +379,10 @@ struct dw_mipi_dsi { > struct clk *pclk; > struct clk *phy_cfg_clk; > > + /* dual-channel */ > + struct dw_mipi_dsi *master; > + struct dw_mipi_dsi *slave; > + > int dpms_mode; > unsigned int lane_mbps; /* per lane */ > u32 channel; > @@ -574,6 +635,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, > unsigned int max_mbps = dptdin_map[ARRAY_SIZE(dptdin_map) - 1].max_mbps; > int bpp; > unsigned long best_freq = 0; > + int lanes = dsi->lanes; > unsigned long fvco_min, fvco_max, fin, fout; > unsigned int min_prediv, max_prediv; > unsigned int _prediv, uninitialized_var(best_prediv); > @@ -587,10 +649,13 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, > return bpp; > } > > + if (dsi->slave || dsi->master) > + lanes = dsi->lanes * 2; > + > mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); > if (mpclk) { > /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ > - tmp = mpclk * (bpp / dsi->lanes) * 10 / 8; > + tmp = mpclk * (bpp / lanes) * 10 / 8; > if (tmp < max_mbps) > target_mbps = tmp; > else > @@ -653,17 +718,26 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, > struct mipi_dsi_device *device) > { > struct dw_mipi_dsi *dsi = host_to_dsi(host); > + int lanes = dsi->slave ? device->lanes / 2 : device->lanes; > > - if (device->lanes > dsi->pdata->max_data_lanes) { > + if (lanes > dsi->pdata->max_data_lanes) { > dev_err(dsi->dev, "the number of data lanes(%u) is too many\n", > - device->lanes); > + lanes); > return -EINVAL; > } > > - dsi->lanes = device->lanes; > + dsi->lanes = lanes; > dsi->channel = device->channel; > dsi->format = device->format; > dsi->mode_flags = device->mode_flags; > + > + if (dsi->slave) { > + dsi->slave->lanes = lanes; > + dsi->slave->channel = device->channel; > + dsi->slave->format = device->format; > + dsi->slave->mode_flags = device->mode_flags; > + } > + > dsi->panel = of_drm_find_panel(device->dev.of_node); > if (dsi->panel) > return drm_panel_attach(dsi->panel, &dsi->connector); > @@ -793,15 +867,22 @@ static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, > int ret; > > dw_mipi_message_config(dsi, msg); > + if (dsi->slave) > + dw_mipi_message_config(dsi->slave, msg); > > switch (msg->type) { > case MIPI_DSI_DCS_SHORT_WRITE: > case MIPI_DSI_DCS_SHORT_WRITE_PARAM: > case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: > + case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: > ret = dw_mipi_dsi_dcs_short_write(dsi, msg); > + if (dsi->slave) > + ret = dw_mipi_dsi_dcs_short_write(dsi->slave, msg); > break; > case MIPI_DSI_DCS_LONG_WRITE: > ret = dw_mipi_dsi_dcs_long_write(dsi, msg); > + if (dsi->slave) > + ret = dw_mipi_dsi_dcs_long_write(dsi->slave, msg); > break; > default: > dev_err(dsi->dev, "unsupported message type 0x%02x\n", > @@ -875,6 +956,55 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) > TX_ESC_CLK_DIVIDSION(esc_clk_division)); > } > > +static void rockchip_dsi_grf_config(struct dw_mipi_dsi *dsi, int vop_id) > +{ > + const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata; > + int val = 0; > + int ret; > + > + /* > + * For the RK3399, the clk of grf must be enabled before writing grf > + * register. And for RK3288 or other soc, this grf_clk must be NULL, > + * the clk_prepare_enable return true directly. > + */ > + ret = clk_prepare_enable(dsi->grf_clk); > + if (ret) { > + dev_err(dsi->dev, "Failed to enable grf_clk: %d\n", ret); > + return; > + } > + > + val = pdata->dsi0_en_bit << 16; > + if (dsi->slave) > + val |= pdata->dsi1_en_bit << 16; > + if (vop_id) { > + val |= pdata->dsi0_en_bit; > + if (dsi->slave) > + val |= pdata->dsi1_en_bit; > + } > + regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val); > + > + if (pdata->grf_dsi0_mode_reg) > + regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg, > + pdata->grf_dsi0_mode); > + > + if (dsi->slave) { > + if (pdata->grf_dsi1_mode_reg1) > + regmap_write(dsi->grf_regmap, pdata->grf_dsi1_mode_reg1, > + pdata->grf_dsi1_mode); > + val = pdata->dsi1_masterslavez | > + (pdata->dsi1_masterslavez << 16) | > + (pdata->dsi1_basedir << 16); val is only used in the if branch below, no need to calculate it when the branch isn't executed. > + if (pdata->grf_dsi1_mode_reg2) > + regmap_write(dsi->grf_regmap, pdata->grf_dsi1_mode_reg2, > + val); > + if (pdata->grf_dsi1_mode_reg1) > + regmap_write(dsi->grf_regmap, pdata->grf_dsi1_mode_reg1, > + pdata->grf_dsi1_enable); > + } > + > + clk_disable_unprepare(dsi->grf_clk); > +} > + > static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, > struct drm_display_mode *mode) > { > @@ -915,7 +1045,14 @@ static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) > static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, > struct drm_display_mode *mode) > { > - dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay)); > + int pkt_size; > + > + if (dsi->slave || dsi->master) > + pkt_size = VID_PKT_SIZE(mode->hdisplay / 2); > + else > + pkt_size = VID_PKT_SIZE(mode->hdisplay); > + > + dsi_write(dsi, DSI_VID_PKT_SIZE, pkt_size); > } > > static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) > @@ -1020,24 +1157,26 @@ static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder) > dw_mipi_dsi_disable(dsi); > pm_runtime_put(dsi->dev); > clk_disable_unprepare(dsi->pclk); > + > + if (dsi->slave) { > + if (clk_prepare_enable(dsi->slave->pclk)) { > + dev_err(dsi->slave->dev, "%s: Failed to enable pclk\n", __func__); > + return; > + } > + dw_mipi_dsi_disable(dsi->slave); > + pm_runtime_put(dsi->slave->dev); > + clk_disable_unprepare(dsi->slave->pclk); > + } > + > dsi->dpms_mode = DRM_MODE_DPMS_OFF; > } > > -static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) > +static void dw_mipi_dsi_enable(struct dw_mipi_dsi *dsi, struct drm_display_mode *mode) > { > - struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder); > - struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; > - const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata; > - int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder); > - u32 val; > - int ret; > - > - ret = dw_mipi_dsi_get_lane_bps(dsi, mode); > - if (ret < 0) > - return; > - > - if (dsi->dpms_mode == DRM_MODE_DPMS_ON) > + if (dw_mipi_dsi_get_lane_bps(dsi, mode) < 0) { > + dev_err(dsi->dev, "%s: Failed to get lane bps\n", __func__); > return; > + } > > if (clk_prepare_enable(dsi->pclk)) { > dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__); > @@ -1057,43 +1196,42 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) > dw_mipi_dsi_dphy_interface_config(dsi); > dw_mipi_dsi_clear_err(dsi); > > - /* > - * For the RK3399, the clk of grf must be enabled before writing grf > - * register. And for RK3288 or other soc, this grf_clk must be NULL, > - * the clk_prepare_enable return true directly. > - */ > - ret = clk_prepare_enable(dsi->grf_clk); > - if (ret) { > - dev_err(dsi->dev, "Failed to enable grf_clk: %d\n", ret); > - return; > - } > - > - if (pdata->grf_dsi0_mode_reg) > - regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg, > - pdata->grf_dsi0_mode); > - > dw_mipi_dsi_phy_init(dsi); > dw_mipi_dsi_wait_for_two_frames(mode); > > dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE); > +} > + > +static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) > +{ > + struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder); > + struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; > + int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder); > + > + if (dsi->dpms_mode == DRM_MODE_DPMS_ON) > + return; > + > + rockchip_dsi_grf_config(dsi, mux); > + dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG"); > + > + dw_mipi_dsi_enable(dsi, mode); > + if (dsi->slave) > + dw_mipi_dsi_enable(dsi->slave, mode); > + > if (drm_panel_prepare(dsi->panel)) > dev_err(dsi->dev, "failed to prepare panel\n"); > > dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE); > + if (dsi->slave) > + dw_mipi_dsi_set_mode(dsi->slave, DW_MIPI_DSI_VID_MODE); > + > drm_panel_enable(dsi->panel); > > clk_disable_unprepare(dsi->pclk); > + if (dsi->slave) > + clk_disable_unprepare(dsi->slave->pclk); > > - if (mux) > - val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16); > - else > - val = pdata->dsi0_en_bit << 16; > - > - regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val); > - dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG"); > dsi->dpms_mode = DRM_MODE_DPMS_ON; > - > - clk_disable_unprepare(dsi->grf_clk); > } > > static int > @@ -1121,6 +1259,9 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) > > s->output_type = DRM_MODE_CONNECTOR_DSI; > > + if (dsi->slave) > + s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL; > + > return 0; > } > > @@ -1226,6 +1367,13 @@ static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi) > .grf_switch_reg = RK3399_GRF_SOC_CON20, > .grf_dsi0_mode = RK3399_GRF_DSI_MODE, > .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22, > + .grf_dsi1_mode = RK3399_GRF_DSI1_MODE, > + .grf_dsi1_enable = RK3399_GRF_DSI1_ENABLE, > + .grf_dsi1_mode_reg1 = RK3399_GRF_SOC_CON23, > + .dsi1_basedir = RK3399_TXRX_BASEDIR, > + .dsi1_masterslavez = RK3399_TXRX_MASTERSLAVEZ, > + .dsi1_enableclk = RK3399_TXRX_ENABLECLK, > + .grf_dsi1_mode_reg2 = RK3399_GRF_SOC_CON24, > .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, > .max_data_lanes = 4, > }; > @@ -1242,17 +1390,107 @@ static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi) > }; > MODULE_DEVICE_TABLE(of, dw_mipi_dsi_dt_ids); > > + > +static int rockchip_dsi_dual_channel_probe(struct dw_mipi_dsi *dsi) > +{ > + struct device_node *np; > + struct platform_device *secondary; > + > + np = of_parse_phandle(dsi->dev->of_node, "rockchip,dual-channel", 0); > + if (np) { > + secondary = of_find_device_by_node(np); > + dsi->slave = platform_get_drvdata(secondary); > + of_node_put(np); > + > + if (!dsi->slave) > + return -EPROBE_DEFER; > + > + dsi->slave->master = dsi; > + } > + > + return 0; > +} > + > static int dw_mipi_dsi_bind(struct device *dev, struct device *master, > void *data) > { > + struct drm_device *drm = data; > + struct dw_mipi_dsi *dsi = dev_get_drvdata(dev); > + int ret; > + > + ret = rockchip_dsi_dual_channel_probe(dsi); > + if (ret) > + return ret; > + > + ret = clk_prepare_enable(dsi->pllref_clk); > + if (ret) { > + dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__); > + return ret; > + } > + > + pm_runtime_enable(dev); > + > + if (dsi->master) > + return 0; > + > + ret = dw_mipi_dsi_register(drm, dsi); > + if (ret) { > + dev_err(dev, "Failed to register mipi_dsi: %d\n", ret); > + goto err_pllref; > + } > + > + dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; > + dsi->dsi_host.dev = dev; > + ret = mipi_dsi_host_register(&dsi->dsi_host); > + if (ret) { > + dev_err(dev, "Failed to register MIPI host: %d\n", ret); > + goto err_cleanup; > + } > + > + if (!dsi->panel) { > + ret = -EPROBE_DEFER; > + goto err_mipi_dsi_host; > + } > + > + return 0; > + > +err_mipi_dsi_host: > + mipi_dsi_host_unregister(&dsi->dsi_host); > +err_cleanup: > + drm_encoder_cleanup(&dsi->encoder); > + drm_connector_cleanup(&dsi->connector); > +err_pllref: > + pm_runtime_disable(dev); > + clk_disable_unprepare(dsi->pllref_clk); > + return ret; > +} > + > +static void dw_mipi_dsi_unbind(struct device *dev, struct device *master, > + void *data) > +{ > + struct dw_mipi_dsi *dsi = dev_get_drvdata(dev); > + > + mipi_dsi_host_unregister(&dsi->dsi_host); > + pm_runtime_disable(dev); > + if (dsi->slave) > + pm_runtime_disable(dsi->slave->dev); > + clk_disable_unprepare(dsi->pllref_clk); > +} > + > +static const struct component_ops dw_mipi_dsi_ops = { > + .bind = dw_mipi_dsi_bind, > + .unbind = dw_mipi_dsi_unbind, > +}; > + > +static int dw_mipi_dsi_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > const struct of_device_id *of_id = > of_match_device(dw_mipi_dsi_dt_ids, dev); > const struct dw_mipi_dsi_plat_data *pdata = of_id->data; > - struct platform_device *pdev = to_platform_device(dev); > - struct reset_control *apb_rst; > - struct drm_device *drm = data; > struct dw_mipi_dsi *dsi; > struct resource *res; > + struct reset_control *apb_rst; > int ret; > > dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); > @@ -1262,6 +1500,7 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, > dsi->dev = dev; > dsi->pdata = pdata; > dsi->dpms_mode = DRM_MODE_DPMS_OFF; > + dev_set_drvdata(dev, dsi); > > ret = rockchip_mipi_parse_dt(dsi); > if (ret) > @@ -1336,63 +1575,6 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, > } > } > > - ret = clk_prepare_enable(dsi->pllref_clk); > - if (ret) { > - dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__); > - return ret; > - } > - > - ret = dw_mipi_dsi_register(drm, dsi); > - if (ret) { > - dev_err(dev, "Failed to register mipi_dsi: %d\n", ret); > - goto err_pllref; > - } > - > - pm_runtime_enable(dev); > - > - dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; > - dsi->dsi_host.dev = dev; > - ret = mipi_dsi_host_register(&dsi->dsi_host); > - if (ret) { > - dev_err(dev, "Failed to register MIPI host: %d\n", ret); > - goto err_cleanup; > - } > - > - if (!dsi->panel) { > - ret = -EPROBE_DEFER; > - goto err_mipi_dsi_host; > - } > - > - dev_set_drvdata(dev, dsi); > - return 0; > - > -err_mipi_dsi_host: > - mipi_dsi_host_unregister(&dsi->dsi_host); > -err_cleanup: > - drm_encoder_cleanup(&dsi->encoder); > - drm_connector_cleanup(&dsi->connector); > -err_pllref: > - clk_disable_unprepare(dsi->pllref_clk); > - return ret; > -} > - > -static void dw_mipi_dsi_unbind(struct device *dev, struct device *master, > - void *data) > -{ > - struct dw_mipi_dsi *dsi = dev_get_drvdata(dev); > - > - mipi_dsi_host_unregister(&dsi->dsi_host); > - pm_runtime_disable(dev); > - clk_disable_unprepare(dsi->pllref_clk); > -} > - > -static const struct component_ops dw_mipi_dsi_ops = { > - .bind = dw_mipi_dsi_bind, > - .unbind = dw_mipi_dsi_unbind, > -}; > - > -static int dw_mipi_dsi_probe(struct platform_device *pdev) > -{ > return component_add(&pdev->dev, &dw_mipi_dsi_ops); > } > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h > index c7e96b8..51ad1c2 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h > @@ -36,6 +36,7 @@ struct rockchip_crtc_state { > struct drm_crtc_state base; > int output_type; > int output_mode; > + int output_flags; > }; > #define to_rockchip_crtc_state(s) \ > container_of(s, struct rockchip_crtc_state, base) > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > index bf9ed0e..cb40cdd 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > @@ -917,6 +917,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, > case DRM_MODE_CONNECTOR_DSI: > VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); > VOP_REG_SET(vop, output, mipi_en, 1); > + VOP_REG_SET(vop, output, mipi_dual_channel_en, > + !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)); > break; > case DRM_MODE_CONNECTOR_DisplayPort: > pin_pol &= ~BIT(DCLK_INVERT); > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h > index 56bbd2e..d184531 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h > @@ -60,6 +60,7 @@ struct vop_output { > struct vop_reg edp_en; > struct vop_reg hdmi_en; > struct vop_reg mipi_en; > + struct vop_reg mipi_dual_channel_en; > struct vop_reg rgb_en; > }; > > @@ -212,6 +213,8 @@ struct vop_data { > /* for use special outface */ > #define ROCKCHIP_OUT_MODE_AAAA 15 > > +#define ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL BIT(0) > + > enum alpha_mode { > ALPHA_STRAIGHT, > ALPHA_INVERSE,