From: Dave Airlie <airlied-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: [PATCH 2/2] drm/amdgpu/vega10: static constify channel_number
Date: Thu, 28 Sep 2017 08:48:32 +1000 [thread overview]
Message-ID: <20170927224832.18088-2-airlied@gmail.com> (raw)
In-Reply-To: <20170927224832.18088-1-airlied-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index a59d282..80e41be 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -56,7 +56,7 @@
#define HBM_MEMORY_CHANNEL_WIDTH 128
-uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
+static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
#define MEM_FREQ_LOW_LATENCY 25000
#define MEM_FREQ_HIGH_LATENCY 80000
--
2.9.4
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next prev parent reply other threads:[~2017-09-27 22:48 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-27 22:48 [PATCH 1/2] drm/amdgpu/pp: constify some powerplay tables Dave Airlie
[not found] ` <20170927224832.18088-1-airlied-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-09-27 22:48 ` Dave Airlie [this message]
2017-09-27 22:53 ` Alex Deucher
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