diff for duplicates of <20170928142050.gkbdqlwpfjmpdlg3@flea> diff --git a/a/1.txt b/N1/1.txt index 566788c..b5e74a4 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,4 +1,4 @@ -On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy@aosc.io wrote: +On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy at aosc.io wrote: > > On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote: > > > The A64 PLL_CPU clock has the same instability if some factor changed > > > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33, @@ -92,3 +92,10 @@ Maxime Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: signature.asc +Type: application/pgp-signature +Size: 801 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170928/d10bc7f2/attachment.sig> diff --git a/a/2.bin b/a/2.bin deleted file mode 100644 index 8248b05..0000000 --- a/a/2.bin +++ /dev/null @@ -1,16 +0,0 @@ ------BEGIN PGP SIGNATURE----- - -iQIcBAEBAgAGBQJZzQVCAAoJEBx+YmzsjxAgWfIP/jVxa/nJyoiocVCqSrz2Sk4z -pRXAByC+Qm6Hx95ZooK43H+BqXOwig32Vjx9X0YKSTDmU4t7giZwOM47/bTeJVsZ -oyfD8h1bjR2wjfBV3KtzEaub5WdzllWWOhy9/T3cg7zuE9fbScpJ2DK+q6f/LwUn -/nQChhHgLJtSoVwyxuRpjXLowB4wB/OsOQXP6vf+x0IK4P/KySaJ5PGbnqFNdxvG -BH5LdZ2YxLOLV/B8ZFXRrEF0eVtIdla9VW4vMwlcO+XIQdwFB4sOWZQTmm9FO0s5 -PaWkLHyzbWleNg7U58lCwBTyRMyGECBVs9A1nsN/dA9Pe9Hgi7/TPcDL1a76gmAL -XFib2wMB8a/MQS5jj5rEiugkBikiyofvLGTNvTPM2EN4m+v1JYMJq4xEpJZhyiQP -ZLLa7aP6y5s2lB3QtpJ5kL0e6PqbAoo1tuHe7vrrhxJssQdiVYtIAn9cTZ9pQeGf -vmgHmEdZAWntTh6qS4h6OB+1OUvbsKvV840w93jiR8sQkBKoqMvp0dp6i9xuw6XJ -f1YWp6x4MH44FnZLQWHySb/azeT1NT6B0l1HhddUwJrUHVYbiE1MtHMUdCJtUn/A -DrmrxSUFbfL9ZnMW13ZxEwjFHepr1uTIu+yy+webGbvfv3uKtlIEz0/ObwnGccwu -EthZxRA6uDCASBGsRNMH -=umA7 ------END PGP SIGNATURE----- diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index 5e5352c..0000000 --- a/a/2.hdr +++ /dev/null @@ -1 +0,0 @@ -Content-Type: application/pgp-signature; name="signature.asc" diff --git a/a/content_digest b/N1/content_digest index d12924a..6cc3d96 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,19 +2,13 @@ "ref\020170923001531.14285-2-icenowy@aosc.io\0" "ref\020170928102752.ceo54qccqakb4xyx@flea\0" "ref\0975c0c884d9a83faad6141df474a93af@aosc.io\0" - "From\0Maxime Ripard <maxime.ripard@free-electrons.com>\0" - "Subject\0Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock\0" + "From\0maxime.ripard@free-electrons.com (Maxime Ripard)\0" + "Subject\0[PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock\0" "Date\0Thu, 28 Sep 2017 16:20:50 +0200\0" - "To\0icenowy@aosc.io\0" - "Cc\0devicetree@vger.kernel.org" - linux-sunxi@googlegroups.com - linux-kernel@vger.kernel.org - Chen-Yu Tsai <wens@csie.org> - linux-clk@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" - "On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy@aosc.io wrote:\n" + "On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy at aosc.io wrote:\n" "> > On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:\n" "> > > The A64 PLL_CPU clock has the same instability if some factor changed\n" "> > > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,\n" @@ -107,25 +101,13 @@ "-- \n" "Maxime Ripard, Free Electrons\n" "Embedded Linux and Kernel engineering\n" - http://free-electrons.com - "\01:2\0" - "fn\0signature.asc\0" - "b\0" - "-----BEGIN PGP SIGNATURE-----\n" - "\n" - "iQIcBAEBAgAGBQJZzQVCAAoJEBx+YmzsjxAgWfIP/jVxa/nJyoiocVCqSrz2Sk4z\n" - "pRXAByC+Qm6Hx95ZooK43H+BqXOwig32Vjx9X0YKSTDmU4t7giZwOM47/bTeJVsZ\n" - "oyfD8h1bjR2wjfBV3KtzEaub5WdzllWWOhy9/T3cg7zuE9fbScpJ2DK+q6f/LwUn\n" - "/nQChhHgLJtSoVwyxuRpjXLowB4wB/OsOQXP6vf+x0IK4P/KySaJ5PGbnqFNdxvG\n" - "BH5LdZ2YxLOLV/B8ZFXRrEF0eVtIdla9VW4vMwlcO+XIQdwFB4sOWZQTmm9FO0s5\n" - "PaWkLHyzbWleNg7U58lCwBTyRMyGECBVs9A1nsN/dA9Pe9Hgi7/TPcDL1a76gmAL\n" - "XFib2wMB8a/MQS5jj5rEiugkBikiyofvLGTNvTPM2EN4m+v1JYMJq4xEpJZhyiQP\n" - "ZLLa7aP6y5s2lB3QtpJ5kL0e6PqbAoo1tuHe7vrrhxJssQdiVYtIAn9cTZ9pQeGf\n" - "vmgHmEdZAWntTh6qS4h6OB+1OUvbsKvV840w93jiR8sQkBKoqMvp0dp6i9xuw6XJ\n" - "f1YWp6x4MH44FnZLQWHySb/azeT1NT6B0l1HhddUwJrUHVYbiE1MtHMUdCJtUn/A\n" - "DrmrxSUFbfL9ZnMW13ZxEwjFHepr1uTIu+yy+webGbvfv3uKtlIEz0/ObwnGccwu\n" - "EthZxRA6uDCASBGsRNMH\n" - "=umA7\n" - "-----END PGP SIGNATURE-----\n" + "http://free-electrons.com\n" + "-------------- next part --------------\n" + "A non-text attachment was scrubbed...\n" + "Name: signature.asc\n" + "Type: application/pgp-signature\n" + "Size: 801 bytes\n" + "Desc: not available\n" + URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170928/d10bc7f2/attachment.sig> -14e0500199f8198c4987ecb6f247e3dbd65c9eed97bcb322a71c95a6058f1e8e +76d957287e6fd50ed6532b88f470ef8b149fd23e0e206b88654b79536d113f7d
diff --git a/a/1.txt b/N2/1.txt index 566788c..586ff76 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,4 +1,4 @@ -On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy@aosc.io wrote: +On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy-h8G6r0blFSE@public.gmane.org wrote: > > On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote: > > > The A64 PLL_CPU clock has the same instability if some factor changed > > > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33, @@ -8,7 +8,7 @@ On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy@aosc.io wrote: > > > problem. > > > > > > Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") -> > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +> > > Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org> > > > --- > > > drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28 > > > +++++++++++++++++++++++++++- diff --git a/a/content_digest b/N2/content_digest index d12924a..7f67e93 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,19 +2,20 @@ "ref\020170923001531.14285-2-icenowy@aosc.io\0" "ref\020170928102752.ceo54qccqakb4xyx@flea\0" "ref\0975c0c884d9a83faad6141df474a93af@aosc.io\0" - "From\0Maxime Ripard <maxime.ripard@free-electrons.com>\0" + "ref\0975c0c884d9a83faad6141df474a93af-h8G6r0blFSE@public.gmane.org\0" + "From\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" "Subject\0Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock\0" "Date\0Thu, 28 Sep 2017 16:20:50 +0200\0" - "To\0icenowy@aosc.io\0" - "Cc\0devicetree@vger.kernel.org" - linux-sunxi@googlegroups.com - linux-kernel@vger.kernel.org - Chen-Yu Tsai <wens@csie.org> - linux-clk@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" + "To\0icenowy-h8G6r0blFSE@public.gmane.org\0" + "Cc\0devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" + linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\01:1\0" "b\0" - "On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy@aosc.io wrote:\n" + "On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy-h8G6r0blFSE@public.gmane.org wrote:\n" "> > On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:\n" "> > > The A64 PLL_CPU clock has the same instability if some factor changed\n" "> > > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,\n" @@ -24,7 +25,7 @@ "> > > problem.\n" "> > > \n" "> > > Fixes: c6a0637460c2 (\"clk: sunxi-ng: Add A64 clocks\")\n" - "> > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>\n" + "> > > Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>\n" "> > > ---\n" "> > > drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28\n" "> > > +++++++++++++++++++++++++++-\n" @@ -128,4 +129,4 @@ "=umA7\n" "-----END PGP SIGNATURE-----\n" -14e0500199f8198c4987ecb6f247e3dbd65c9eed97bcb322a71c95a6058f1e8e +d2765dbf61d0650ccc41ffe9f4293759bebde77276f78758205fe505c919cfe6
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