diff for duplicates of <20170929072207.GA12773@ulmo> diff --git a/a/1.txt b/N1/1.txt index 709fdd5..a3914d3 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -4,13 +4,13 @@ On Thu, Sep 28, 2017 at 09:57:19PM -0500, Bjorn Helgaas wrote: > > > Inline... > > > > > > On Sat, Sep 23, 2017 at 11:47 AM, Thierry Reding -> > > <thierry.reding@gmail.com> wrote: +> > > <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > > > > > > > > The Tegra20 PCIe controller has a different address range for MSI, so > > > > select a different target address. > > > > > > > > Fixes: d7bd554f27c9 ("PCI: tegra: Do not allocate MSI target memory") -> > > > Signed-off-by: Thierry Reding <treding@nvidia.com> +> > > > Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > > > --- > > > > drivers/pci/host/pci-tegra.c | 12 +++++++++++- > > > > 1 file changed, 11 insertions(+), 1 deletion(-) @@ -126,7 +126,7 @@ some broader coverage, though. Thierry --- >8 --- From 36108b8facc443170f91d64bb8d6bed79f5de0ba Mon Sep 17 00:00:00 2001 -From: Thierry Reding <treding@nvidia.com> +From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Date: Wed, 27 Sep 2017 11:42:31 +0200 Subject: [PATCH] PCI: tegra: Enable the use of 32-bit MSI @@ -141,8 +141,8 @@ configuration could redefine the regions to include the new MSI target addresses, doing so shouldn't cause any issues because this memory is not actually accessed by MSI. -Reported-by: Vidya Sagar <vidias@nvidia.com> -Signed-off-by: Thierry Reding <treding@nvidia.com> +Reported-by: Vidya Sagar <vidias-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- drivers/pci/host/pci-tegra.c | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/a/content_digest b/N1/content_digest index 72a3981..aed3793 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,16 +2,17 @@ "ref\0CAN7O0+JyG3XT5SsWGsiZs0vrk0ha1vQ5N7rjYxs3tM_NvdONdw@mail.gmail.com\0" "ref\020170928141912.GB28022@ulmo\0" "ref\020170929025719.GZ15970@bhelgaas-glaptop.roam.corp.google.com\0" - "From\0Thierry Reding <thierry.reding@gmail.com>\0" + "ref\020170929025719.GZ15970-1RhO1Y9PlrlHTL0Zs8A6p5iNqAH0jzoTYJqu5kTmcBRl57MIdRCFDg@public.gmane.org\0" + "From\0Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" "Subject\0Re: [PATCH] PCI: tegra: Use different MSI target address for Tegra20\0" "Date\0Fri, 29 Sep 2017 09:22:07 +0200\0" - "To\0Bjorn Helgaas <helgaas@kernel.org>\0" - "Cc\0vidya sagar <sagar.tv@gmail.com>" - Bjorn Helgaas <bhelgaas@google.com> - Jonathan Hunter <jonathanh@nvidia.com> - Mikko Perttunen <mperttunen@nvidia.com> - linux-pci@vger.kernel.org - " linux-tegra@vger.kernel.org\0" + "To\0Bjorn Helgaas <helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\0" + "Cc\0vidya sagar <sagar.tv-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>" + Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org> + Jonathan Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> + Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> + linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\01:1\0" "b\0" "On Thu, Sep 28, 2017 at 09:57:19PM -0500, Bjorn Helgaas wrote:\n" @@ -20,13 +21,13 @@ "> > > Inline...\n" "> > > \n" "> > > On Sat, Sep 23, 2017 at 11:47 AM, Thierry Reding\n" - "> > > <thierry.reding@gmail.com> wrote:\n" + "> > > <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:\n" "> > > >\n" "> > > > The Tegra20 PCIe controller has a different address range for MSI, so\n" "> > > > select a different target address.\n" "> > > >\n" "> > > > Fixes: d7bd554f27c9 (\"PCI: tegra: Do not allocate MSI target memory\")\n" - "> > > > Signed-off-by: Thierry Reding <treding@nvidia.com>\n" + "> > > > Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "> > > > ---\n" "> > > > drivers/pci/host/pci-tegra.c | 12 +++++++++++-\n" "> > > > 1 file changed, 11 insertions(+), 1 deletion(-)\n" @@ -142,7 +143,7 @@ "Thierry\n" "--- >8 ---\n" "From 36108b8facc443170f91d64bb8d6bed79f5de0ba Mon Sep 17 00:00:00 2001\n" - "From: Thierry Reding <treding@nvidia.com>\n" + "From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "Date: Wed, 27 Sep 2017 11:42:31 +0200\n" "Subject: [PATCH] PCI: tegra: Enable the use of 32-bit MSI\n" "\n" @@ -157,8 +158,8 @@ "addresses, doing so shouldn't cause any issues because this memory is\n" "not actually accessed by MSI.\n" "\n" - "Reported-by: Vidya Sagar <vidias@nvidia.com>\n" - "Signed-off-by: Thierry Reding <treding@nvidia.com>\n" + "Reported-by: Vidya Sagar <vidias-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + "Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "---\n" " drivers/pci/host/pci-tegra.c | 38 ++++++++++++++++++++------------------\n" " 1 file changed, 20 insertions(+), 18 deletions(-)\n" @@ -272,4 +273,4 @@ "=NwQT\n" "-----END PGP SIGNATURE-----\n" -a280eaf5597a26cce4cd6b52d23d13d2dafa50954ab25bc9c714b2677d4d3fbb +999c983de50bc43452296d896d8898670d0f40e3a0fc1d06ddf9e1c2f7bc378b
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.