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From: "Lothar Waßmann" <LW@KARO-electronics.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] imx: serial: Wait for ongoing transmission to finish before serial reset
Date: Wed, 4 Oct 2017 09:05:00 +0200	[thread overview]
Message-ID: <20171004090500.1b4585bd@karo-electronics.de> (raw)
In-Reply-To: <1507022205-11877-1-git-send-email-lukma@denx.de>

Hi,

On Tue,  3 Oct 2017 11:16:45 +0200 Lukasz Majewski wrote:
> It may happen that the MXC serial IP block is performing some ongoing
> transmission (started at e.g. board_init()) when the "initr_serial" is
> called.
> 
> As a result the serial port IP block is reset, so transmitted data is
> corrupted:
> 
> I2C:   ready
> DRAM:  1 GiB
> jSS('HH��SL_SDHC: 04 rev 0x0
> 
> This patch prevents from this situation, by waiting for transmission
> complete bit set (UART Status Register 2 (UARTx_USR2), bit TXDC):
> 
> I2C:   ready
> DRAM:  1 GiB
> ID:    unit type 0x4 rev 0x0
> 
> Signed-off-by: Lukasz Majewski <lukma@denx.de>
> ---
> 
>  drivers/serial/serial_mxc.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
> index cce80a8..ef4eb12 100644
> --- a/drivers/serial/serial_mxc.c
> +++ b/drivers/serial/serial_mxc.c
> @@ -141,6 +141,13 @@ struct mxc_uart {
>  
>  static void _mxc_serial_init(struct mxc_uart *base)
>  {
> +	/*
> +	 * Wait for any ongoing transmission to finish - for example
> +	 * from pre-relocation enabled UART
> +	 */
> +	while (!(readl(&base->sr2) & USR2_TXDC))
> +		;
> +
>
Loops that poll for HW activated bits should always have a timeout.
Hardware will definitely break some day and deliver unexpected results.
Software should cope with this as best as it can!


Lothar Waßmann

  parent reply	other threads:[~2017-10-04  7:05 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-03  9:16 [U-Boot] [PATCH] imx: serial: Wait for ongoing transmission to finish before serial reset Lukasz Majewski
2017-10-03  9:30 ` Stefano Babic
2017-10-04  7:05 ` Lothar Waßmann [this message]
2017-10-04  8:21   ` Łukasz Majewski
2017-10-09  4:48 ` Simon Glass
2017-10-09 10:46   ` Łukasz Majewski
2017-10-22 14:33     ` Simon Glass

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