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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id z204sm1815883lff.33.2017.10.10.07.48.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 10 Oct 2017 07:48:35 -0700 (PDT) Date: Tue, 10 Oct 2017 16:48:34 +0200 From: "Edgar E. Iglesias" To: Alistair Francis Message-ID: <20171010144834.GC5553@toto> References: <20171008222029.GA29979@toto> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::234 Subject: Re: [Qemu-arm] [PATCH v3 0/8] Add the ZynqMP PMU and IPI X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , qemu-arm , "qemu-devel@nongnu.org Developers" Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: +K0zaodUsDeK On Mon, Oct 09, 2017 at 05:12:39PM -0700, Alistair Francis wrote: > On Sun, Oct 8, 2017 at 3:20 PM, Edgar E. Iglesias > wrote: > > On Wed, Sep 20, 2017 at 03:01:31PM -0700, Alistair Francis wrote: > >> > >> This series adds the ZynqMP Power Management Unit (PMU) machine with basic > >> functionality. > >> > >> The machine only has the > >> - CPU > >> - Memory > >> - Interrupt controller > >> - IPI device > >> > >> connected, but that is enough to run some of the ROM and firmware > >> code on the machine > >> > >> The series also adds the IPI device and connects it to the ZynqMP ARM > >> side and the ZynqMP PMU. These IPI devices don't connect between the ARM > >> and MicroBlaze instances though. > >> > >> v3: > >> - Add the interrupt controller > >> - Replace some of the error_fatals with errp > >> - Fix the PMU CPU name > > > > Hi Alistair, > > > > > > Sorry for the super long delay... > > > > I think this mostly looks good but I was wondering if we really need > > to have a board specific (zcu102) PMU? > > It doesn't have to be board specific. What I wanted though was an SoC > and a machine so that maybe one day we could add the PMU SoC to the > ARM ZCU102 machine. After that it was hard to think of a name to > differentiate the SoC and the machine. Do you have a recommendation on > names? Hi Alistair, Yes, I agree with your approach but I got a little confused by the names. I think all the stuff that is inside the PMU subsystem architecture-wise should have generic PMU names (no ZCU102). I.e the ROM, the RAM, the IOModule, interrupt controller etc. The IPI block can be outside of the PMU module and be instantiated by the board or perhaps better if we could reuse some of the ZynqMP modules instantiated by the ZCU102 machine to get a CPU-less PS for the PMU to interact with. Or something along those lines. How does that sound? Best regards, Edgar From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57554) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1vpq-0001jy-LA for qemu-devel@nongnu.org; Tue, 10 Oct 2017 10:48:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1vpn-0005ud-Ey for qemu-devel@nongnu.org; Tue, 10 Oct 2017 10:48:42 -0400 Date: Tue, 10 Oct 2017 16:48:34 +0200 From: "Edgar E. Iglesias" Message-ID: <20171010144834.GC5553@toto> References: <20171008222029.GA29979@toto> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v3 0/8] Add the ZynqMP PMU and IPI List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alistair Francis Cc: "Edgar E. Iglesias" , "qemu-devel@nongnu.org Developers" , qemu-arm On Mon, Oct 09, 2017 at 05:12:39PM -0700, Alistair Francis wrote: > On Sun, Oct 8, 2017 at 3:20 PM, Edgar E. Iglesias > wrote: > > On Wed, Sep 20, 2017 at 03:01:31PM -0700, Alistair Francis wrote: > >> > >> This series adds the ZynqMP Power Management Unit (PMU) machine with basic > >> functionality. > >> > >> The machine only has the > >> - CPU > >> - Memory > >> - Interrupt controller > >> - IPI device > >> > >> connected, but that is enough to run some of the ROM and firmware > >> code on the machine > >> > >> The series also adds the IPI device and connects it to the ZynqMP ARM > >> side and the ZynqMP PMU. These IPI devices don't connect between the ARM > >> and MicroBlaze instances though. > >> > >> v3: > >> - Add the interrupt controller > >> - Replace some of the error_fatals with errp > >> - Fix the PMU CPU name > > > > Hi Alistair, > > > > > > Sorry for the super long delay... > > > > I think this mostly looks good but I was wondering if we really need > > to have a board specific (zcu102) PMU? > > It doesn't have to be board specific. What I wanted though was an SoC > and a machine so that maybe one day we could add the PMU SoC to the > ARM ZCU102 machine. After that it was hard to think of a name to > differentiate the SoC and the machine. Do you have a recommendation on > names? Hi Alistair, Yes, I agree with your approach but I got a little confused by the names. I think all the stuff that is inside the PMU subsystem architecture-wise should have generic PMU names (no ZCU102). I.e the ROM, the RAM, the IOModule, interrupt controller etc. The IPI block can be outside of the PMU module and be instantiated by the board or perhaps better if we could reuse some of the ZynqMP modules instantiated by the ZCU102 machine to get a CPU-less PS for the PMU to interact with. Or something along those lines. How does that sound? Best regards, Edgar