[PATCH v8 0/4] Add support for ThunderX2 pmu events using json files

[PATCH v8 0/4] Add support for ThunderX2 pmu events using json files

[Ganapatrao Kulkarni]

Extending json/jevent framework for parsing arm64 event files.
Adding jevents for ThunderX2 implementation defined PMU events.

v8:
   - Rename thunderx2 directory to cavium

v7:
   - Addressed some more comments from Will Deacon.

v6 : Addressed comments [1] [2]

[1] https://patchwork.kernel.org/patch/9903099/
[2] https://patchwork.kernel.org/patch/9853899/

v5:
   - Addressed comments from Arnaldo.
   - Rebased to 4.13-rc5

v4:
   - Rebased to 4.13-rc1

v3:
   - Addressed comments from Will Deacon and Jayachandran C.
   - Rebased to 4.12-rc1

v2:
   - Updated as per Mark Rutland's suggestions.
   - Added provision for get_cpuid_str to get cpu id string
     from associated cpus of pmu core device.

v1: Initial patchset.

Ganapatrao Kulkarni (4):
  perf utils: passing pmu as a parameter to function get_cpuid_str
  perf tools arm64: Add support for get_cpuid_str function.
  perf utils: Add helper function is_pmu_core to detect PMU CORE devices
  perf vendor events arm64: Add ThunderX2 implementation defined pmu
    core events

 tools/perf/arch/arm64/util/Build                   |  1 +
 tools/perf/arch/arm64/util/header.c                | 65 ++++++++++++++++++++++
 tools/perf/arch/powerpc/util/header.c              |  2 +-
 tools/perf/arch/x86/util/header.c                  |  2 +-
 .../arch/arm64/cavium/thunderx2-imp-def.json       | 62 +++++++++++++++++++++
 tools/perf/pmu-events/arch/arm64/mapfile.csv       | 15 +++++
 tools/perf/util/header.h                           |  3 +-
 tools/perf/util/pmu.c                              | 52 +++++++++++++----
 8 files changed, 189 insertions(+), 13 deletions(-)
 create mode 100644 tools/perf/arch/arm64/util/header.c
 create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv

-- 
2.9.4

[PATCH v8 0/4] Add support for ThunderX2 pmu events using json files

[Ganapatrao Kulkarni]

Extending json/jevent framework for parsing arm64 event files.
Adding jevents for ThunderX2 implementation defined PMU events.

v8:
   - Rename thunderx2 directory to cavium

v7:
   - Addressed some more comments from Will Deacon.

v6 : Addressed comments [1] [2]

[1] https://patchwork.kernel.org/patch/9903099/
[2] https://patchwork.kernel.org/patch/9853899/

v5:
   - Addressed comments from Arnaldo.
   - Rebased to 4.13-rc5

v4:
   - Rebased to 4.13-rc1

v3:
   - Addressed comments from Will Deacon and Jayachandran C.
   - Rebased to 4.12-rc1

v2:
   - Updated as per Mark Rutland's suggestions.
   - Added provision for get_cpuid_str to get cpu id string
     from associated cpus of pmu core device.

v1: Initial patchset.

Ganapatrao Kulkarni (4):
  perf utils: passing pmu as a parameter to function get_cpuid_str
  perf tools arm64: Add support for get_cpuid_str function.
  perf utils: Add helper function is_pmu_core to detect PMU CORE devices
  perf vendor events arm64: Add ThunderX2 implementation defined pmu
    core events

 tools/perf/arch/arm64/util/Build                   |  1 +
 tools/perf/arch/arm64/util/header.c                | 65 ++++++++++++++++++++++
 tools/perf/arch/powerpc/util/header.c              |  2 +-
 tools/perf/arch/x86/util/header.c                  |  2 +-
 .../arch/arm64/cavium/thunderx2-imp-def.json       | 62 +++++++++++++++++++++
 tools/perf/pmu-events/arch/arm64/mapfile.csv       | 15 +++++
 tools/perf/util/header.h                           |  3 +-
 tools/perf/util/pmu.c                              | 52 +++++++++++++----
 8 files changed, 189 insertions(+), 13 deletions(-)
 create mode 100644 tools/perf/arch/arm64/util/header.c
 create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv

-- 
2.9.4

[PATCH v8 1/4] perf utils: passing pmu as a parameter to function get_cpuid_str

[Ganapatrao Kulkarni]

cpuid string will not be same on all CPUs on heterogeneous
platforms like ARM's big.LITTLE, adding provision(using pmu->cpus)
to find cpuid string from associated CPUs of PMU CORE device.

also optimise arguments to function pmu_add_cpu_aliases.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 tools/perf/arch/powerpc/util/header.c |  2 +-
 tools/perf/arch/x86/util/header.c     |  2 +-
 tools/perf/util/header.h              |  3 ++-
 tools/perf/util/pmu.c                 | 13 +++++++------
 4 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/tools/perf/arch/powerpc/util/header.c b/tools/perf/arch/powerpc/util/header.c
index 9aaa6f5..2953681 100644
--- a/tools/perf/arch/powerpc/util/header.c
+++ b/tools/perf/arch/powerpc/util/header.c
@@ -34,7 +34,7 @@ get_cpuid(char *buffer, size_t sz)
 }
 
 char *
-get_cpuid_str(void)
+get_cpuid_str(struct perf_pmu *pmu __maybe_unused)
 {
 	char *bufp;
 
diff --git a/tools/perf/arch/x86/util/header.c b/tools/perf/arch/x86/util/header.c
index a74a48d..d52bc27 100644
--- a/tools/perf/arch/x86/util/header.c
+++ b/tools/perf/arch/x86/util/header.c
@@ -65,7 +65,7 @@ get_cpuid(char *buffer, size_t sz)
 }
 
 char *
-get_cpuid_str(void)
+get_cpuid_str(struct perf_pmu *pmu __maybe_unused)
 {
 	char *buf = malloc(128);
 
diff --git a/tools/perf/util/header.h b/tools/perf/util/header.h
index f7a16ee..3de4be9 100644
--- a/tools/perf/util/header.h
+++ b/tools/perf/util/header.h
@@ -8,6 +8,7 @@
 #include <linux/types.h>
 #include "event.h"
 #include "env.h"
+#include "pmu.h"
 
 enum {
 	HEADER_RESERVED		= 0,	/* always cleared */
@@ -165,5 +166,5 @@ int write_padded(struct feat_fd *fd, const void *bf,
  */
 int get_cpuid(char *buffer, size_t sz);
 
-char *get_cpuid_str(void);
+char *get_cpuid_str(struct perf_pmu *pmu __maybe_unused);
 #endif /* __PERF_HEADER_H */
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index ac16a9d..18edf86 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -511,7 +511,7 @@ static struct cpu_map *pmu_cpumask(const char *name)
  * Each architecture should provide a more precise id string that
  * can be use to match the architecture's "mapfile".
  */
-char * __weak get_cpuid_str(void)
+char * __weak get_cpuid_str(struct perf_pmu *pmu __maybe_unused)
 {
 	return NULL;
 }
@@ -521,19 +521,20 @@ char * __weak get_cpuid_str(void)
  * to the current running CPU. Then, add all PMU events from that table
  * as aliases.
  */
-static void pmu_add_cpu_aliases(struct list_head *head, const char *name)
+static void pmu_add_cpu_aliases(struct list_head *head, struct perf_pmu *pmu)
 {
 	int i;
 	struct pmu_events_map *map;
 	struct pmu_event *pe;
 	char *cpuid;
 	static bool printed;
+	const char *name = pmu->name;
 
 	cpuid = getenv("PERF_CPUID");
 	if (cpuid)
 		cpuid = strdup(cpuid);
 	if (!cpuid)
-		cpuid = get_cpuid_str();
+		cpuid = get_cpuid_str(pmu);
 	if (!cpuid)
 		return;
 
@@ -610,19 +611,19 @@ static struct perf_pmu *pmu_lookup(const char *name)
 	if (pmu_aliases(name, &aliases))
 		return NULL;
 
-	pmu_add_cpu_aliases(&aliases, name);
 	pmu = zalloc(sizeof(*pmu));
 	if (!pmu)
 		return NULL;
 
 	pmu->cpus = pmu_cpumask(name);
+	pmu->name = strdup(name);
+	pmu->type = type;
+	pmu_add_cpu_aliases(&aliases, pmu);
 
 	INIT_LIST_HEAD(&pmu->format);
 	INIT_LIST_HEAD(&pmu->aliases);
 	list_splice(&format, &pmu->format);
 	list_splice(&aliases, &pmu->aliases);
-	pmu->name = strdup(name);
-	pmu->type = type;
 	list_add_tail(&pmu->list, &pmus);
 
 	pmu->default_config = perf_pmu__get_default_config(pmu);
-- 
2.9.4

[PATCH v8 1/4] perf utils: passing pmu as a parameter to function get_cpuid_str

[Ganapatrao Kulkarni]

cpuid string will not be same on all CPUs on heterogeneous
platforms like ARM's big.LITTLE, adding provision(using pmu->cpus)
to find cpuid string from associated CPUs of PMU CORE device.

also optimise arguments to function pmu_add_cpu_aliases.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 tools/perf/arch/powerpc/util/header.c |  2 +-
 tools/perf/arch/x86/util/header.c     |  2 +-
 tools/perf/util/header.h              |  3 ++-
 tools/perf/util/pmu.c                 | 13 +++++++------
 4 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/tools/perf/arch/powerpc/util/header.c b/tools/perf/arch/powerpc/util/header.c
index 9aaa6f5..2953681 100644
--- a/tools/perf/arch/powerpc/util/header.c
+++ b/tools/perf/arch/powerpc/util/header.c
@@ -34,7 +34,7 @@ get_cpuid(char *buffer, size_t sz)
 }
 
 char *
-get_cpuid_str(void)
+get_cpuid_str(struct perf_pmu *pmu __maybe_unused)
 {
 	char *bufp;
 
diff --git a/tools/perf/arch/x86/util/header.c b/tools/perf/arch/x86/util/header.c
index a74a48d..d52bc27 100644
--- a/tools/perf/arch/x86/util/header.c
+++ b/tools/perf/arch/x86/util/header.c
@@ -65,7 +65,7 @@ get_cpuid(char *buffer, size_t sz)
 }
 
 char *
-get_cpuid_str(void)
+get_cpuid_str(struct perf_pmu *pmu __maybe_unused)
 {
 	char *buf = malloc(128);
 
diff --git a/tools/perf/util/header.h b/tools/perf/util/header.h
index f7a16ee..3de4be9 100644
--- a/tools/perf/util/header.h
+++ b/tools/perf/util/header.h
@@ -8,6 +8,7 @@
 #include <linux/types.h>
 #include "event.h"
 #include "env.h"
+#include "pmu.h"
 
 enum {
 	HEADER_RESERVED		= 0,	/* always cleared */
@@ -165,5 +166,5 @@ int write_padded(struct feat_fd *fd, const void *bf,
  */
 int get_cpuid(char *buffer, size_t sz);
 
-char *get_cpuid_str(void);
+char *get_cpuid_str(struct perf_pmu *pmu __maybe_unused);
 #endif /* __PERF_HEADER_H */
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index ac16a9d..18edf86 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -511,7 +511,7 @@ static struct cpu_map *pmu_cpumask(const char *name)
  * Each architecture should provide a more precise id string that
  * can be use to match the architecture's "mapfile".
  */
-char * __weak get_cpuid_str(void)
+char * __weak get_cpuid_str(struct perf_pmu *pmu __maybe_unused)
 {
 	return NULL;
 }
@@ -521,19 +521,20 @@ char * __weak get_cpuid_str(void)
  * to the current running CPU. Then, add all PMU events from that table
  * as aliases.
  */
-static void pmu_add_cpu_aliases(struct list_head *head, const char *name)
+static void pmu_add_cpu_aliases(struct list_head *head, struct perf_pmu *pmu)
 {
 	int i;
 	struct pmu_events_map *map;
 	struct pmu_event *pe;
 	char *cpuid;
 	static bool printed;
+	const char *name = pmu->name;
 
 	cpuid = getenv("PERF_CPUID");
 	if (cpuid)
 		cpuid = strdup(cpuid);
 	if (!cpuid)
-		cpuid = get_cpuid_str();
+		cpuid = get_cpuid_str(pmu);
 	if (!cpuid)
 		return;
 
@@ -610,19 +611,19 @@ static struct perf_pmu *pmu_lookup(const char *name)
 	if (pmu_aliases(name, &aliases))
 		return NULL;
 
-	pmu_add_cpu_aliases(&aliases, name);
 	pmu = zalloc(sizeof(*pmu));
 	if (!pmu)
 		return NULL;
 
 	pmu->cpus = pmu_cpumask(name);
+	pmu->name = strdup(name);
+	pmu->type = type;
+	pmu_add_cpu_aliases(&aliases, pmu);
 
 	INIT_LIST_HEAD(&pmu->format);
 	INIT_LIST_HEAD(&pmu->aliases);
 	list_splice(&format, &pmu->format);
 	list_splice(&aliases, &pmu->aliases);
-	pmu->name = strdup(name);
-	pmu->type = type;
 	list_add_tail(&pmu->list, &pmus);
 
 	pmu->default_config = perf_pmu__get_default_config(pmu);
-- 
2.9.4

[PATCH v8 2/4] perf tools arm64: Add support for get_cpuid_str function.

[Ganapatrao Kulkarni]

function get_cpuid_str returns MIDR string of the first online
cpu from the range of cpus associated with the pmu core device.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 tools/perf/arch/arm64/util/Build    |  1 +
 tools/perf/arch/arm64/util/header.c | 65 +++++++++++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+)
 create mode 100644 tools/perf/arch/arm64/util/header.c

diff --git a/tools/perf/arch/arm64/util/Build b/tools/perf/arch/arm64/util/Build
index cef6fb3..b1ab72d 100644
--- a/tools/perf/arch/arm64/util/Build
+++ b/tools/perf/arch/arm64/util/Build
@@ -1,3 +1,4 @@
+libperf-y += header.o
 libperf-$(CONFIG_DWARF)     += dwarf-regs.o
 libperf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
 
diff --git a/tools/perf/arch/arm64/util/header.c b/tools/perf/arch/arm64/util/header.c
new file mode 100644
index 0000000..74567d7
--- /dev/null
+++ b/tools/perf/arch/arm64/util/header.c
@@ -0,0 +1,65 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <api/fs/fs.h>
+#include "header.h"
+
+#define MIDR "/regs/identification/midr_el1"
+#define MIDR_SIZE 19
+#define MIDR_REVISION_MASK      0xf
+#define MIDR_VARIANT_SHIFT      20
+#define MIDR_VARIANT_MASK       (0xf << MIDR_VARIANT_SHIFT)
+
+char *get_cpuid_str(struct perf_pmu *pmu)
+{
+	char *buf = NULL;
+	char path[PATH_MAX];
+	const char *sysfs = sysfs__mountpoint();
+	int cpu;
+	u64 midr = 0;
+	struct cpu_map *cpus;
+	FILE *file;
+
+	if (!sysfs || !pmu->cpus)
+		return NULL;
+
+	buf = malloc(MIDR_SIZE);
+	if (!buf)
+		return NULL;
+
+	/* read midr from list of cpus mapped to this pmu */
+	cpus = cpu_map__get(pmu->cpus);
+	for (cpu = 0; cpu < cpus->nr; cpu++) {
+		scnprintf(path, PATH_MAX, "%s/devices/system/cpu/cpu%d"MIDR,
+				sysfs, cpus->map[cpu]);
+
+		file = fopen(path, "r");
+		if (!file) {
+			pr_debug("fopen failed for file %s\n", path);
+			continue;
+		}
+
+		if (!fgets(buf, MIDR_SIZE, file)) {
+			fclose(file);
+			continue;
+		}
+		fclose(file);
+
+		/* Ignore/clear Variant[23:20] and
+		 * Revision[3:0] of MIDR
+		 */
+		midr = strtoul(buf, NULL, 16);
+		midr &= (~(MIDR_VARIANT_MASK | MIDR_REVISION_MASK));
+		scnprintf(buf, MIDR_SIZE, "0x%016lx", midr);
+		/* got midr break loop */
+		break;
+	}
+
+	if (!midr) {
+		pr_err("failed to get cpuid string for PMU %s\n", pmu->name);
+		free(buf);
+		buf = NULL;
+	}
+
+	cpu_map__put(cpus);
+	return buf;
+}
-- 
2.9.4

[PATCH v8 2/4] perf tools arm64: Add support for get_cpuid_str function.

[Ganapatrao Kulkarni]

function get_cpuid_str returns MIDR string of the first online
cpu from the range of cpus associated with the pmu core device.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 tools/perf/arch/arm64/util/Build    |  1 +
 tools/perf/arch/arm64/util/header.c | 65 +++++++++++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+)
 create mode 100644 tools/perf/arch/arm64/util/header.c

diff --git a/tools/perf/arch/arm64/util/Build b/tools/perf/arch/arm64/util/Build
index cef6fb3..b1ab72d 100644
--- a/tools/perf/arch/arm64/util/Build
+++ b/tools/perf/arch/arm64/util/Build
@@ -1,3 +1,4 @@
+libperf-y += header.o
 libperf-$(CONFIG_DWARF)     += dwarf-regs.o
 libperf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
 
diff --git a/tools/perf/arch/arm64/util/header.c b/tools/perf/arch/arm64/util/header.c
new file mode 100644
index 0000000..74567d7
--- /dev/null
+++ b/tools/perf/arch/arm64/util/header.c
@@ -0,0 +1,65 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <api/fs/fs.h>
+#include "header.h"
+
+#define MIDR "/regs/identification/midr_el1"
+#define MIDR_SIZE 19
+#define MIDR_REVISION_MASK      0xf
+#define MIDR_VARIANT_SHIFT      20
+#define MIDR_VARIANT_MASK       (0xf << MIDR_VARIANT_SHIFT)
+
+char *get_cpuid_str(struct perf_pmu *pmu)
+{
+	char *buf = NULL;
+	char path[PATH_MAX];
+	const char *sysfs = sysfs__mountpoint();
+	int cpu;
+	u64 midr = 0;
+	struct cpu_map *cpus;
+	FILE *file;
+
+	if (!sysfs || !pmu->cpus)
+		return NULL;
+
+	buf = malloc(MIDR_SIZE);
+	if (!buf)
+		return NULL;
+
+	/* read midr from list of cpus mapped to this pmu */
+	cpus = cpu_map__get(pmu->cpus);
+	for (cpu = 0; cpu < cpus->nr; cpu++) {
+		scnprintf(path, PATH_MAX, "%s/devices/system/cpu/cpu%d"MIDR,
+				sysfs, cpus->map[cpu]);
+
+		file = fopen(path, "r");
+		if (!file) {
+			pr_debug("fopen failed for file %s\n", path);
+			continue;
+		}
+
+		if (!fgets(buf, MIDR_SIZE, file)) {
+			fclose(file);
+			continue;
+		}
+		fclose(file);
+
+		/* Ignore/clear Variant[23:20] and
+		 * Revision[3:0] of MIDR
+		 */
+		midr = strtoul(buf, NULL, 16);
+		midr &= (~(MIDR_VARIANT_MASK | MIDR_REVISION_MASK));
+		scnprintf(buf, MIDR_SIZE, "0x%016lx", midr);
+		/* got midr break loop */
+		break;
+	}
+
+	if (!midr) {
+		pr_err("failed to get cpuid string for PMU %s\n", pmu->name);
+		free(buf);
+		buf = NULL;
+	}
+
+	cpu_map__put(cpus);
+	return buf;
+}
-- 
2.9.4

[PATCH v8 3/4] perf utils: Add helper function is_pmu_core to detect PMU CORE devices

[Ganapatrao Kulkarni]

On some platforms, PMU core devices sysfs name is not cpu.
Adding function is_pmu_core to detect PMU core devices using
core device specific hints in sysfs.

For arm64 platforms, all core devices have file "cpus" in sysfs.

Acked-by: Will Deacon <will.deacon@arm.com>
Tested-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 tools/perf/util/pmu.c | 39 +++++++++++++++++++++++++++++++++++----
 1 file changed, 35 insertions(+), 4 deletions(-)

diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index 18edf86..153f92d 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -506,6 +506,34 @@ static struct cpu_map *pmu_cpumask(const char *name)
 }
 
 /*
+ *  PMU CORE devices have different name other than cpu in sysfs on some
+ *  platforms. looking for possible sysfs files to identify as core device.
+ */
+static int is_pmu_core(const char *name)
+{
+	struct stat st;
+	char path[PATH_MAX];
+	const char *sysfs = sysfs__mountpoint();
+
+	if (!sysfs)
+		return 0;
+
+	/* Look for cpu sysfs (x86 and others) */
+	scnprintf(path, PATH_MAX, "%s/bus/event_source/devices/cpu", sysfs);
+	if ((stat(path, &st) == 0) &&
+			(strncmp(name, "cpu", strlen("cpu")) == 0))
+		return 1;
+
+	/* Look for cpu sysfs (specific to arm) */
+	scnprintf(path, PATH_MAX, "%s/bus/event_source/devices/%s/cpus",
+				sysfs, name);
+	if (stat(path, &st) == 0)
+		return 1;
+
+	return 0;
+}
+
+/*
  * Return the CPU id as a raw string.
  *
  * Each architecture should provide a more precise id string that
@@ -558,15 +586,18 @@ static void pmu_add_cpu_aliases(struct list_head *head, struct perf_pmu *pmu)
 	 */
 	i = 0;
 	while (1) {
-		const char *pname;
 
 		pe = &map->table[i++];
 		if (!pe->name)
 			break;
 
-		pname = pe->pmu ? pe->pmu : "cpu";
-		if (strncmp(pname, name, strlen(pname)))
-			continue;
+		if (!is_pmu_core(name)) {
+			/* check for uncore devices */
+			if (pe->pmu == NULL)
+				continue;
+			if (strncmp(pe->pmu, name, strlen(pe->pmu)))
+				continue;
+		}
 
 		/* need type casts to override 'const' */
 		__perf_pmu__new_alias(head, NULL, (char *)pe->name,
-- 
2.9.4

[PATCH v8 3/4] perf utils: Add helper function is_pmu_core to detect PMU CORE devices

[Ganapatrao Kulkarni]

On some platforms, PMU core devices sysfs name is not cpu.
Adding function is_pmu_core to detect PMU core devices using
core device specific hints in sysfs.

For arm64 platforms, all core devices have file "cpus" in sysfs.

Acked-by: Will Deacon <will.deacon@arm.com>
Tested-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 tools/perf/util/pmu.c | 39 +++++++++++++++++++++++++++++++++++----
 1 file changed, 35 insertions(+), 4 deletions(-)

diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index 18edf86..153f92d 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -506,6 +506,34 @@ static struct cpu_map *pmu_cpumask(const char *name)
 }
 
 /*
+ *  PMU CORE devices have different name other than cpu in sysfs on some
+ *  platforms. looking for possible sysfs files to identify as core device.
+ */
+static int is_pmu_core(const char *name)
+{
+	struct stat st;
+	char path[PATH_MAX];
+	const char *sysfs = sysfs__mountpoint();
+
+	if (!sysfs)
+		return 0;
+
+	/* Look for cpu sysfs (x86 and others) */
+	scnprintf(path, PATH_MAX, "%s/bus/event_source/devices/cpu", sysfs);
+	if ((stat(path, &st) == 0) &&
+			(strncmp(name, "cpu", strlen("cpu")) == 0))
+		return 1;
+
+	/* Look for cpu sysfs (specific to arm) */
+	scnprintf(path, PATH_MAX, "%s/bus/event_source/devices/%s/cpus",
+				sysfs, name);
+	if (stat(path, &st) == 0)
+		return 1;
+
+	return 0;
+}
+
+/*
  * Return the CPU id as a raw string.
  *
  * Each architecture should provide a more precise id string that
@@ -558,15 +586,18 @@ static void pmu_add_cpu_aliases(struct list_head *head, struct perf_pmu *pmu)
 	 */
 	i = 0;
 	while (1) {
-		const char *pname;
 
 		pe = &map->table[i++];
 		if (!pe->name)
 			break;
 
-		pname = pe->pmu ? pe->pmu : "cpu";
-		if (strncmp(pname, name, strlen(pname)))
-			continue;
+		if (!is_pmu_core(name)) {
+			/* check for uncore devices */
+			if (pe->pmu == NULL)
+				continue;
+			if (strncmp(pe->pmu, name, strlen(pe->pmu)))
+				continue;
+		}
 
 		/* need type casts to override 'const' */
 		__perf_pmu__new_alias(head, NULL, (char *)pe->name,
-- 
2.9.4

[PATCH v8 4/4] perf vendor events arm64: Add ThunderX2 implementation defined pmu core events

[Ganapatrao Kulkarni]

This is not a full event list, but a short list of useful events.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 .../arch/arm64/cavium/thunderx2-imp-def.json       | 62 ++++++++++++++++++++++
 tools/perf/pmu-events/arch/arm64/mapfile.csv       | 15 ++++++
 2 files changed, 77 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv

diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
new file mode 100644
index 0000000..2db45c4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
@@ -0,0 +1,62 @@
+[
+    {
+        "PublicDescription": "Attributable Level 1 data cache access, read",
+        "EventCode": "0x40",
+        "EventName": "l1d_cache_rd",
+        "BriefDescription": "L1D cache read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache access, write ",
+        "EventCode": "0x41",
+        "EventName": "l1d_cache_wr",
+        "BriefDescription": "L1D cache write",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache refill, read",
+        "EventCode": "0x42",
+        "EventName": "l1d_cache_refill_rd",
+        "BriefDescription": "L1D cache refill read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache refill, write",
+        "EventCode": "0x43",
+        "EventName": "l1d_cache_refill_wr",
+        "BriefDescription": "L1D refill write",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data TLB refill, read",
+        "EventCode": "0x4C",
+        "EventName": "l1d_tlb_refill_rd",
+        "BriefDescription": "L1D tlb refill read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data TLB refill, write",
+        "EventCode": "0x4D",
+        "EventName": "l1d_tlb_refill_wr",
+        "BriefDescription": "L1D tlb refill write",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+        "EventCode": "0x4E",
+        "EventName": "l1d_tlb_rd",
+        "BriefDescription": "L1D tlb read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+        "EventCode": "0x4F",
+        "EventName": "l1d_tlb_wr",
+        "BriefDescription": "L1D tlb write",
+    },
+    {
+        "PublicDescription": "Bus access read",
+        "EventCode": "0x60",
+        "EventName": "bus_access_rd",
+        "BriefDescription": "Bus access read",
+   },
+   {
+        "PublicDescription": "Bus access write",
+        "EventCode": "0x61",
+        "EventName": "bus_access_wr",
+        "BriefDescription": "Bus access write",
+   }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
new file mode 100644
index 0000000..219d675
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -0,0 +1,15 @@
+# Format:
+#	MIDR,Version,JSON/file/pathname,Type
+#
+# where
+#	MIDR	Processor version
+#		Variant[23:20] and Revision [3:0] should be zero.
+#	Version could be used to track version of of JSON file
+#		but currently unused.
+#	JSON/file/pathname is the path to JSON file, relative
+#		to tools/perf/pmu-events/arch/arm64/.
+#	Type is core, uncore etc
+#
+#
+#Family-model,Version,Filename,EventType
+0x00000000420f5160,v1,cavium,core
-- 
2.9.4

[PATCH v8 4/4] perf vendor events arm64: Add ThunderX2 implementation defined pmu core events

[Ganapatrao Kulkarni]

This is not a full event list, but a short list of useful events.

Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
 .../arch/arm64/cavium/thunderx2-imp-def.json       | 62 ++++++++++++++++++++++
 tools/perf/pmu-events/arch/arm64/mapfile.csv       | 15 ++++++
 2 files changed, 77 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv

diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
new file mode 100644
index 0000000..2db45c4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json
@@ -0,0 +1,62 @@
+[
+    {
+        "PublicDescription": "Attributable Level 1 data cache access, read",
+        "EventCode": "0x40",
+        "EventName": "l1d_cache_rd",
+        "BriefDescription": "L1D cache read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache access, write ",
+        "EventCode": "0x41",
+        "EventName": "l1d_cache_wr",
+        "BriefDescription": "L1D cache write",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache refill, read",
+        "EventCode": "0x42",
+        "EventName": "l1d_cache_refill_rd",
+        "BriefDescription": "L1D cache refill read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data cache refill, write",
+        "EventCode": "0x43",
+        "EventName": "l1d_cache_refill_wr",
+        "BriefDescription": "L1D refill write",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data TLB refill, read",
+        "EventCode": "0x4C",
+        "EventName": "l1d_tlb_refill_rd",
+        "BriefDescription": "L1D tlb refill read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data TLB refill, write",
+        "EventCode": "0x4D",
+        "EventName": "l1d_tlb_refill_wr",
+        "BriefDescription": "L1D tlb refill write",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+        "EventCode": "0x4E",
+        "EventName": "l1d_tlb_rd",
+        "BriefDescription": "L1D tlb read",
+    },
+    {
+        "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+        "EventCode": "0x4F",
+        "EventName": "l1d_tlb_wr",
+        "BriefDescription": "L1D tlb write",
+    },
+    {
+        "PublicDescription": "Bus access read",
+        "EventCode": "0x60",
+        "EventName": "bus_access_rd",
+        "BriefDescription": "Bus access read",
+   },
+   {
+        "PublicDescription": "Bus access write",
+        "EventCode": "0x61",
+        "EventName": "bus_access_wr",
+        "BriefDescription": "Bus access write",
+   }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
new file mode 100644
index 0000000..219d675
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -0,0 +1,15 @@
+# Format:
+#	MIDR,Version,JSON/file/pathname,Type
+#
+# where
+#	MIDR	Processor version
+#		Variant[23:20] and Revision [3:0] should be zero.
+#	Version could be used to track version of of JSON file
+#		but currently unused.
+#	JSON/file/pathname is the path to JSON file, relative
+#		to tools/perf/pmu-events/arch/arm64/.
+#	Type is core, uncore etc
+#
+#
+#Family-model,Version,Filename,EventType
+0x00000000420f5160,v1,cavium,core
-- 
2.9.4

[PATCH v8 0/4] Add support for ThunderX2 pmu events using json files

[Will Deacon]

On Thu, Oct 12, 2017 at 07:41:12PM +0530, Ganapatrao Kulkarni wrote:
> Extending json/jevent framework for parsing arm64 event files.
> Adding jevents for ThunderX2 implementation defined PMU events.
> 
> v8:
>    - Rename thunderx2 directory to cavium

For the series:

Acked-by: Will Deacon <will.deacon@arm.com>

Although note that this conflicts against a queued fix from Mark[1], so
you'll need to rebase on top of that.

Will

[1] https://patchwork.kernel.org/patch/9990237/

Re: [PATCH v8 0/4] Add support for ThunderX2 pmu events using json files

[Will Deacon]

On Thu, Oct 12, 2017 at 07:41:12PM +0530, Ganapatrao Kulkarni wrote:
> Extending json/jevent framework for parsing arm64 event files.
> Adding jevents for ThunderX2 implementation defined PMU events.
> 
> v8:
>    - Rename thunderx2 directory to cavium

For the series:

Acked-by: Will Deacon <will.deacon@arm.com>

Although note that this conflicts against a queued fix from Mark[1], so
you'll need to rebase on top of that.

Will

[1] https://patchwork.kernel.org/patch/9990237/

[PATCH v8 0/4] Add support for ThunderX2 pmu events using json files

[Ganapatrao Kulkarni]

On Thu, Oct 12, 2017 at 8:54 PM, Will Deacon <will.deacon@arm.com> wrote:
> On Thu, Oct 12, 2017 at 07:41:12PM +0530, Ganapatrao Kulkarni wrote:
>> Extending json/jevent framework for parsing arm64 event files.
>> Adding jevents for ThunderX2 implementation defined PMU events.
>>
>> v8:
>>    - Rename thunderx2 directory to cavium
>
> For the series:
>
> Acked-by: Will Deacon <will.deacon@arm.com>

thanks.
>
> Although note that this conflicts against a queued fix from Mark[1], so
> you'll need to rebase on top of that.

sure, will do.
may i know the branch/repo which i can rebase to?

>
> Will
>
> [1] https://patchwork.kernel.org/patch/9990237/

thanks
Ganapat

Re: [PATCH v8 0/4] Add support for ThunderX2 pmu events using json files

[Ganapatrao Kulkarni]

On Thu, Oct 12, 2017 at 8:54 PM, Will Deacon <will.deacon@arm.com> wrote:
> On Thu, Oct 12, 2017 at 07:41:12PM +0530, Ganapatrao Kulkarni wrote:
>> Extending json/jevent framework for parsing arm64 event files.
>> Adding jevents for ThunderX2 implementation defined PMU events.
>>
>> v8:
>>    - Rename thunderx2 directory to cavium
>
> For the series:
>
> Acked-by: Will Deacon <will.deacon@arm.com>

thanks.
>
> Although note that this conflicts against a queued fix from Mark[1], so
> you'll need to rebase on top of that.

sure, will do.
may i know the branch/repo which i can rebase to?

>
> Will
>
> [1] https://patchwork.kernel.org/patch/9990237/

thanks
Ganapat

[PATCH v8 0/4] Add support for ThunderX2 pmu events using json files

[Will Deacon]

On Thu, Oct 12, 2017 at 10:54:50PM +0530, Ganapatrao Kulkarni wrote:
> On Thu, Oct 12, 2017 at 8:54 PM, Will Deacon <will.deacon@arm.com> wrote:
> > On Thu, Oct 12, 2017 at 07:41:12PM +0530, Ganapatrao Kulkarni wrote:
> >> Extending json/jevent framework for parsing arm64 event files.
> >> Adding jevents for ThunderX2 implementation defined PMU events.
> >>
> >> v8:
> >>    - Rename thunderx2 directory to cavium
> >
> > For the series:
> >
> > Acked-by: Will Deacon <will.deacon@arm.com>
> 
> thanks.
> >
> > Although note that this conflicts against a queued fix from Mark[1], so
> > you'll need to rebase on top of that.
> 
> sure, will do.
> may i know the branch/repo which i can rebase to?

Arnaldo said he was going to apply it to his perf/urgent branch [1],
although I can't spot it there yet. I'm also not sure whether that's the
right thing on which to base 4.15 material. Arnaldo -- what's the best
thing to do here?

Cheers,

Will

[1] http://lkml.kernel.org/r/20171009190000.GL2121 at redhat.com

Re: [PATCH v8 0/4] Add support for ThunderX2 pmu events using json files

[Will Deacon]

On Thu, Oct 12, 2017 at 10:54:50PM +0530, Ganapatrao Kulkarni wrote:
> On Thu, Oct 12, 2017 at 8:54 PM, Will Deacon <will.deacon@arm.com> wrote:
> > On Thu, Oct 12, 2017 at 07:41:12PM +0530, Ganapatrao Kulkarni wrote:
> >> Extending json/jevent framework for parsing arm64 event files.
> >> Adding jevents for ThunderX2 implementation defined PMU events.
> >>
> >> v8:
> >>    - Rename thunderx2 directory to cavium
> >
> > For the series:
> >
> > Acked-by: Will Deacon <will.deacon@arm.com>
> 
> thanks.
> >
> > Although note that this conflicts against a queued fix from Mark[1], so
> > you'll need to rebase on top of that.
> 
> sure, will do.
> may i know the branch/repo which i can rebase to?

Arnaldo said he was going to apply it to his perf/urgent branch [1],
although I can't spot it there yet. I'm also not sure whether that's the
right thing on which to base 4.15 material. Arnaldo -- what's the best
thing to do here?

Cheers,

Will

[1] http://lkml.kernel.org/r/20171009190000.GL2121@redhat.com

[PATCH v8 0/4] Add support for ThunderX2 pmu events using json files

[Arnaldo Carvalho de Melo]

Em Fri, Oct 13, 2017 at 10:11:42AM +0100, Will Deacon escreveu:
> On Thu, Oct 12, 2017 at 10:54:50PM +0530, Ganapatrao Kulkarni wrote:
> > On Thu, Oct 12, 2017 at 8:54 PM, Will Deacon <will.deacon@arm.com> wrote:
> > > On Thu, Oct 12, 2017 at 07:41:12PM +0530, Ganapatrao Kulkarni wrote:
> > >> Extending json/jevent framework for parsing arm64 event files.
> > >> Adding jevents for ThunderX2 implementation defined PMU events.
> > >>
> > >> v8:
> > >>    - Rename thunderx2 directory to cavium
> > >
> > > For the series:
> > >
> > > Acked-by: Will Deacon <will.deacon@arm.com>
> > 
> > thanks.
> > >
> > > Although note that this conflicts against a queued fix from Mark[1], so
> > > you'll need to rebase on top of that.
> > 
> > sure, will do.
> > may i know the branch/repo which i can rebase to?
> 
> Arnaldo said he was going to apply it to his perf/urgent branch [1],

It is already in tip/perf/urgent, on its way to Linus:

[acme at jouet linux]$ git log -7 --oneline tip/perf/urgent
47a74bdcbfef (HEAD -> perf/urgent, tip/perf/urgent) Merge tag 'perf-urgent-for-mingo-4.14-20171010' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent
629eb703d3e4 perf/x86/intel/uncore: Fix memory leaks on allocation failures
e6a5203399d1 perf/core: Fix cgroup time when scheduling descendants
df0062b27ebf perf/core: Avoid freeing static PMU contexts when PMU is unregistered
aa7b4e02b328 (tag: perf-urgent-for-mingo-4.14-20171010) tools include uapi bpf.h: Sync kernel ABI header with tooling header
66ec11919a0f perf pmu: Unbreak perf record for arm/arm64 with events with explicit PMU
e9516c0813ae (tag: perf-urgent-for-mingo-4.14-20171006, acme/perf/urgent, acme.korg/perf/urgent) perf script: Add missing separator for "-F ip,brstack" (and brstackoff)
[acme at jouet linux]$

> although I can't spot it there yet. I'm also not sure whether that's the
> right thing on which to base 4.15 material. Arnaldo -- what's the best
> thing to do here?

I'll read about the json bits now.
 
> Cheers,
> 
> Will
> 
> [1] http://lkml.kernel.org/r/20171009190000.GL2121 at redhat.com

Re: [PATCH v8 0/4] Add support for ThunderX2 pmu events using json files

[Arnaldo Carvalho de Melo]

Em Fri, Oct 13, 2017 at 10:11:42AM +0100, Will Deacon escreveu:
> On Thu, Oct 12, 2017 at 10:54:50PM +0530, Ganapatrao Kulkarni wrote:
> > On Thu, Oct 12, 2017 at 8:54 PM, Will Deacon <will.deacon@arm.com> wrote:
> > > On Thu, Oct 12, 2017 at 07:41:12PM +0530, Ganapatrao Kulkarni wrote:
> > >> Extending json/jevent framework for parsing arm64 event files.
> > >> Adding jevents for ThunderX2 implementation defined PMU events.
> > >>
> > >> v8:
> > >>    - Rename thunderx2 directory to cavium
> > >
> > > For the series:
> > >
> > > Acked-by: Will Deacon <will.deacon@arm.com>
> > 
> > thanks.
> > >
> > > Although note that this conflicts against a queued fix from Mark[1], so
> > > you'll need to rebase on top of that.
> > 
> > sure, will do.
> > may i know the branch/repo which i can rebase to?
> 
> Arnaldo said he was going to apply it to his perf/urgent branch [1],

It is already in tip/perf/urgent, on its way to Linus:

[acme@jouet linux]$ git log -7 --oneline tip/perf/urgent
47a74bdcbfef (HEAD -> perf/urgent, tip/perf/urgent) Merge tag 'perf-urgent-for-mingo-4.14-20171010' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent
629eb703d3e4 perf/x86/intel/uncore: Fix memory leaks on allocation failures
e6a5203399d1 perf/core: Fix cgroup time when scheduling descendants
df0062b27ebf perf/core: Avoid freeing static PMU contexts when PMU is unregistered
aa7b4e02b328 (tag: perf-urgent-for-mingo-4.14-20171010) tools include uapi bpf.h: Sync kernel ABI header with tooling header
66ec11919a0f perf pmu: Unbreak perf record for arm/arm64 with events with explicit PMU
e9516c0813ae (tag: perf-urgent-for-mingo-4.14-20171006, acme/perf/urgent, acme.korg/perf/urgent) perf script: Add missing separator for "-F ip,brstack" (and brstackoff)
[acme@jouet linux]$

> although I can't spot it there yet. I'm also not sure whether that's the
> right thing on which to base 4.15 material. Arnaldo -- what's the best
> thing to do here?

I'll read about the json bits now.
 
> Cheers,
> 
> Will
> 
> [1] http://lkml.kernel.org/r/20171009190000.GL2121@redhat.com

[PATCH v8 0/4] Add support for ThunderX2 pmu events using json files

[Arnaldo Carvalho de Melo]

Em Fri, Oct 13, 2017 at 10:04:43AM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Fri, Oct 13, 2017 at 10:11:42AM +0100, Will Deacon escreveu:
> > On Thu, Oct 12, 2017 at 10:54:50PM +0530, Ganapatrao Kulkarni wrote:
> > > On Thu, Oct 12, 2017 at 8:54 PM, Will Deacon <will.deacon@arm.com> wrote:
> > > > On Thu, Oct 12, 2017 at 07:41:12PM +0530, Ganapatrao Kulkarni wrote:
> > > >> Extending json/jevent framework for parsing arm64 event files.
> > > >> Adding jevents for ThunderX2 implementation defined PMU events.
> > > >>
> > > >> v8:
> > > >>    - Rename thunderx2 directory to cavium
> > > >
> > > > For the series:
> > > >
> > > > Acked-by: Will Deacon <will.deacon@arm.com>
> > > 
> > > thanks.
> > > >
> > > > Although note that this conflicts against a queued fix from Mark[1], so
> > > > you'll need to rebase on top of that.
> > > 
> > > sure, will do.
> > > may i know the branch/repo which i can rebase to?
> > 
> > Arnaldo said he was going to apply it to his perf/urgent branch [1],
> 
> It is already in tip/perf/urgent, on its way to Linus:
> 
> [acme at jouet linux]$ git log -7 --oneline tip/perf/urgent
> 47a74bdcbfef (HEAD -> perf/urgent, tip/perf/urgent) Merge tag 'perf-urgent-for-mingo-4.14-20171010' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent
> 629eb703d3e4 perf/x86/intel/uncore: Fix memory leaks on allocation failures
> e6a5203399d1 perf/core: Fix cgroup time when scheduling descendants
> df0062b27ebf perf/core: Avoid freeing static PMU contexts when PMU is unregistered
> aa7b4e02b328 (tag: perf-urgent-for-mingo-4.14-20171010) tools include uapi bpf.h: Sync kernel ABI header with tooling header
> 66ec11919a0f perf pmu: Unbreak perf record for arm/arm64 with events with explicit PMU
> e9516c0813ae (tag: perf-urgent-for-mingo-4.14-20171006, acme/perf/urgent, acme.korg/perf/urgent) perf script: Add missing separator for "-F ip,brstack" (and brstackoff)
> [acme at jouet linux]$
> 
> > although I can't spot it there yet. I'm also not sure whether that's the
> > right thing on which to base 4.15 material. Arnaldo -- what's the best
> > thing to do here?
> 
> I'll read about the json bits now.

Ok, I merged tip/perf/urgent into acme/perf/core, can you please rebase
from there and check that everything is ok?

Thanks,

- Arnaldo

Re: [PATCH v8 0/4] Add support for ThunderX2 pmu events using json files

[Arnaldo Carvalho de Melo]

Em Fri, Oct 13, 2017 at 10:04:43AM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Fri, Oct 13, 2017 at 10:11:42AM +0100, Will Deacon escreveu:
> > On Thu, Oct 12, 2017 at 10:54:50PM +0530, Ganapatrao Kulkarni wrote:
> > > On Thu, Oct 12, 2017 at 8:54 PM, Will Deacon <will.deacon@arm.com> wrote:
> > > > On Thu, Oct 12, 2017 at 07:41:12PM +0530, Ganapatrao Kulkarni wrote:
> > > >> Extending json/jevent framework for parsing arm64 event files.
> > > >> Adding jevents for ThunderX2 implementation defined PMU events.
> > > >>
> > > >> v8:
> > > >>    - Rename thunderx2 directory to cavium
> > > >
> > > > For the series:
> > > >
> > > > Acked-by: Will Deacon <will.deacon@arm.com>
> > > 
> > > thanks.
> > > >
> > > > Although note that this conflicts against a queued fix from Mark[1], so
> > > > you'll need to rebase on top of that.
> > > 
> > > sure, will do.
> > > may i know the branch/repo which i can rebase to?
> > 
> > Arnaldo said he was going to apply it to his perf/urgent branch [1],
> 
> It is already in tip/perf/urgent, on its way to Linus:
> 
> [acme@jouet linux]$ git log -7 --oneline tip/perf/urgent
> 47a74bdcbfef (HEAD -> perf/urgent, tip/perf/urgent) Merge tag 'perf-urgent-for-mingo-4.14-20171010' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/urgent
> 629eb703d3e4 perf/x86/intel/uncore: Fix memory leaks on allocation failures
> e6a5203399d1 perf/core: Fix cgroup time when scheduling descendants
> df0062b27ebf perf/core: Avoid freeing static PMU contexts when PMU is unregistered
> aa7b4e02b328 (tag: perf-urgent-for-mingo-4.14-20171010) tools include uapi bpf.h: Sync kernel ABI header with tooling header
> 66ec11919a0f perf pmu: Unbreak perf record for arm/arm64 with events with explicit PMU
> e9516c0813ae (tag: perf-urgent-for-mingo-4.14-20171006, acme/perf/urgent, acme.korg/perf/urgent) perf script: Add missing separator for "-F ip,brstack" (and brstackoff)
> [acme@jouet linux]$
> 
> > although I can't spot it there yet. I'm also not sure whether that's the
> > right thing on which to base 4.15 material. Arnaldo -- what's the best
> > thing to do here?
> 
> I'll read about the json bits now.

Ok, I merged tip/perf/urgent into acme/perf/core, can you please rebase
from there and check that everything is ok?

Thanks,

- Arnaldo