From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris Brezillon Subject: Re: [PATCH v2] drm/vc4: Fix sleeps during the IRQ handler for DSI transactions. Date: Sat, 14 Oct 2017 09:53:55 +0200 Message-ID: <20171014095355.0d9945c9@bbrezillon> References: <20171014001255.32005-1-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail.free-electrons.com (mail.free-electrons.com [62.4.15.54]) by gabe.freedesktop.org (Postfix) with ESMTP id 7FEEF6E275 for ; Sat, 14 Oct 2017 07:53:57 +0000 (UTC) In-Reply-To: <20171014001255.32005-1-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Eric Anholt Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org T24gRnJpLCAxMyBPY3QgMjAxNyAxNzoxMjo1NSAtMDcwMApFcmljIEFuaG9sdCA8ZXJpY0Bhbmhv bHQubmV0PiB3cm90ZToKCj4gVkM0J3MgRFNJMSBoYXMgYSBidWcgd2hlcmUgdGhlIEFYSSBjb25u ZWN0aW9uIGlzIGJyb2tlbiBmb3IgMzItYml0Cj4gd3JpdGVzIGZyb20gdGhlIENQVSwgc28gd2Ug dXNlIHRoZSBETUEgZW5naW5lIHRvIERNQSAzMi1iaXQgdmFsdWVzCj4gaW50byByZWdpc3RlcnMg aW5zdGVhZC4gIFRoYXQgc2xlZXBzLCBzbyB3ZSBjYW4ndCBkbyBpdCBmcm9tIHRoZSB0b3AKPiBo YWxmLgo+IAo+IEFzIGEgc29sdXRpb24sIHVzZSBhbiBpbnRlcnJ1cHQgdGhyZWFkIHNvIHRoYXQg YWxsIG91ciB3cml0ZXMgaGFwcGVuCj4gd2hlbiBzbGVlcGluZyBpcyBpcyBhbGxvd2VkLgo+IAo+ IHYyOiBVc2UgSVJRRl9PTkVTSE9UIChzdWdnZXN0ZWQgYnkgQm9yaXMpCj4gCj4gU2lnbmVkLW9m Zi1ieTogRXJpYyBBbmhvbHQgPGVyaWNAYW5ob2x0Lm5ldD4KClJldmlld2VkLWJ5OiBCb3JpcyBC cmV6aWxsb24gPGJvcmlzLmJyZXppbGxvbkBmcmVlLWVsZWN0cm9ucy5jb20+Cgo+IC0tLQo+IAo+ IEJvcmlzLCB0aGF0IGNsZWFudXAgZW5kZWQgdXAgd29ya2luZyBhbmQgaXQgbG9va3MgZ3JlYXQu ICBUaGFua3MhCj4gCj4gIGRyaXZlcnMvZ3B1L2RybS92YzQvdmM0X2RzaS5jIHwgMzEgKysrKysr KysrKysrKysrKysrKysrKysrKysrKystLQo+ICAxIGZpbGUgY2hhbmdlZCwgMjkgaW5zZXJ0aW9u cygrKSwgMiBkZWxldGlvbnMoLSkKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3Zj NC92YzRfZHNpLmMgYi9kcml2ZXJzL2dwdS9kcm0vdmM0L3ZjNF9kc2kuYwo+IGluZGV4IDU1NDYw NWFmMzQ0ZS4uM2I3NGZkYTU2NjJkIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS92YzQv dmM0X2RzaS5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL3ZjNC92YzRfZHNpLmMKPiBAQCAtMTM2 MCw2ICsxMzYwLDI1IEBAIHN0YXRpYyB2b2lkIGRzaV9oYW5kbGVfZXJyb3Ioc3RydWN0IHZjNF9k c2kgKmRzaSwKPiAgCSpyZXQgPSBJUlFfSEFORExFRDsKPiAgfQo+ICAKPiArLyogSW5pdGlhbCBo YW5kbGVyIGZvciBwb3J0IDEgd2hlcmUgd2UgbmVlZCB0aGUgcmVnX2RtYSB3b3JrYXJvdW5kLgo+ ICsgKiBUaGUgcmVnaXN0ZXIgRE1BIHdyaXRlcyBzbGVlcCwgc28gd2UgY2FuJ3QgZG8gaXQgaW4g dGhlIHRvcCBoYWxmLgo+ICsgKiBJbnN0ZWFkIHdlIHVzZSBJUlFGX09ORVNIT1Qgc28gdGhhdCB0 aGUgSVJRIGdldHMgZGlzYWJsZWQgaW4gdGhlCj4gKyAqIHBhcmVudCBpbnRlcnJ1cHQgY29udHJs bGVyIHVudGlsIG91ciBpbnRlcnJ1cHQgdGhyZWFkIGlzIGRvbmUuCj4gKyAqLwo+ICtzdGF0aWMg aXJxcmV0dXJuX3QgdmM0X2RzaV9pcnFfZGVmZXJfdG9fdGhyZWFkX2hhbmRsZXIoaW50IGlycSwg dm9pZCAqZGF0YSkKPiArewo+ICsJc3RydWN0IHZjNF9kc2kgKmRzaSA9IGRhdGE7Cj4gKwl1MzIg c3RhdCA9IERTSV9QT1JUX1JFQUQoSU5UX1NUQVQpOwo+ICsKPiArCWlmICghc3RhdCkKPiArCQly ZXR1cm4gSVJRX05PTkU7Cj4gKwo+ICsJcmV0dXJuIElSUV9XQUtFX1RIUkVBRDsKPiArfQo+ICsK PiArLyogTm9ybWFsIElSUSBoYW5kbGVyIGZvciBwb3J0IDAsIG9yIHRoZSB0aHJlYWRlZCBJUlEg aGFuZGxlciBmb3IgcG9ydAo+ICsgKiAxIHdoZXJlIHdlIG5lZWQgdGhlIHJlZ19kbWEgd29ya2Fy b3VuZC4KPiArICovCj4gIHN0YXRpYyBpcnFyZXR1cm5fdCB2YzRfZHNpX2lycV9oYW5kbGVyKGlu dCBpcnEsIHZvaWQgKmRhdGEpCj4gIHsKPiAgCXN0cnVjdCB2YzRfZHNpICpkc2kgPSBkYXRhOwo+ IEBAIC0xNTM5LDggKzE1NTgsMTYgQEAgc3RhdGljIGludCB2YzRfZHNpX2JpbmQoc3RydWN0IGRl dmljZSAqZGV2LCBzdHJ1Y3QgZGV2aWNlICptYXN0ZXIsIHZvaWQgKmRhdGEpCj4gIAkvKiBDbGVh ciBhbnkgZXhpc3RpbmcgaW50ZXJydXB0IHN0YXRlLiAqLwo+ICAJRFNJX1BPUlRfV1JJVEUoSU5U X1NUQVQsIERTSV9QT1JUX1JFQUQoSU5UX1NUQVQpKTsKPiAgCj4gLQlyZXQgPSBkZXZtX3JlcXVl c3RfaXJxKGRldiwgcGxhdGZvcm1fZ2V0X2lycShwZGV2LCAwKSwKPiAtCQkJICAgICAgIHZjNF9k c2lfaXJxX2hhbmRsZXIsIDAsICJ2YzQgZHNpIiwgZHNpKTsKPiArCWlmIChkc2ktPnJlZ19kbWFf bWVtKSB7Cj4gKwkJcmV0ID0gZGV2bV9yZXF1ZXN0X3RocmVhZGVkX2lycShkZXYsIHBsYXRmb3Jt X2dldF9pcnEocGRldiwgMCksCj4gKwkJCQkJCXZjNF9kc2lfaXJxX2RlZmVyX3RvX3RocmVhZF9o YW5kbGVyLAo+ICsJCQkJCQl2YzRfZHNpX2lycV9oYW5kbGVyLAo+ICsJCQkJCQlJUlFGX09ORVNI T1QsCj4gKwkJCQkJCSJ2YzQgZHNpIiwgZHNpKTsKPiArCX0gZWxzZSB7Cj4gKwkJcmV0ID0gZGV2 bV9yZXF1ZXN0X2lycShkZXYsIHBsYXRmb3JtX2dldF9pcnEocGRldiwgMCksCj4gKwkJCQkgICAg ICAgdmM0X2RzaV9pcnFfaGFuZGxlciwgMCwgInZjNCBkc2kiLCBkc2kpOwo+ICsJfQo+ICAJaWYg KHJldCkgewo+ICAJCWlmIChyZXQgIT0gLUVQUk9CRV9ERUZFUikKPiAgCQkJZGV2X2VycihkZXYs ICJGYWlsZWQgdG8gZ2V0IGludGVycnVwdDogJWRcbiIsIHJldCk7CgpfX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRy aS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5v cmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751724AbdJNHx7 (ORCPT ); Sat, 14 Oct 2017 03:53:59 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:45519 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750970AbdJNHx6 (ORCPT ); Sat, 14 Oct 2017 03:53:58 -0400 Date: Sat, 14 Oct 2017 09:53:55 +0200 From: Boris Brezillon To: Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] drm/vc4: Fix sleeps during the IRQ handler for DSI transactions. Message-ID: <20171014095355.0d9945c9@bbrezillon> In-Reply-To: <20171014001255.32005-1-eric@anholt.net> References: <20171014001255.32005-1-eric@anholt.net> X-Mailer: Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 13 Oct 2017 17:12:55 -0700 Eric Anholt wrote: > VC4's DSI1 has a bug where the AXI connection is broken for 32-bit > writes from the CPU, so we use the DMA engine to DMA 32-bit values > into registers instead. That sleeps, so we can't do it from the top > half. > > As a solution, use an interrupt thread so that all our writes happen > when sleeping is is allowed. > > v2: Use IRQF_ONESHOT (suggested by Boris) > > Signed-off-by: Eric Anholt Reviewed-by: Boris Brezillon > --- > > Boris, that cleanup ended up working and it looks great. Thanks! > > drivers/gpu/drm/vc4/vc4_dsi.c | 31 +++++++++++++++++++++++++++++-- > 1 file changed, 29 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c > index 554605af344e..3b74fda5662d 100644 > --- a/drivers/gpu/drm/vc4/vc4_dsi.c > +++ b/drivers/gpu/drm/vc4/vc4_dsi.c > @@ -1360,6 +1360,25 @@ static void dsi_handle_error(struct vc4_dsi *dsi, > *ret = IRQ_HANDLED; > } > > +/* Initial handler for port 1 where we need the reg_dma workaround. > + * The register DMA writes sleep, so we can't do it in the top half. > + * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the > + * parent interrupt contrller until our interrupt thread is done. > + */ > +static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data) > +{ > + struct vc4_dsi *dsi = data; > + u32 stat = DSI_PORT_READ(INT_STAT); > + > + if (!stat) > + return IRQ_NONE; > + > + return IRQ_WAKE_THREAD; > +} > + > +/* Normal IRQ handler for port 0, or the threaded IRQ handler for port > + * 1 where we need the reg_dma workaround. > + */ > static irqreturn_t vc4_dsi_irq_handler(int irq, void *data) > { > struct vc4_dsi *dsi = data; > @@ -1539,8 +1558,16 @@ static int vc4_dsi_bind(struct device *dev, struct device *master, void *data) > /* Clear any existing interrupt state. */ > DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT)); > > - ret = devm_request_irq(dev, platform_get_irq(pdev, 0), > - vc4_dsi_irq_handler, 0, "vc4 dsi", dsi); > + if (dsi->reg_dma_mem) { > + ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), > + vc4_dsi_irq_defer_to_thread_handler, > + vc4_dsi_irq_handler, > + IRQF_ONESHOT, > + "vc4 dsi", dsi); > + } else { > + ret = devm_request_irq(dev, platform_get_irq(pdev, 0), > + vc4_dsi_irq_handler, 0, "vc4 dsi", dsi); > + } > if (ret) { > if (ret != -EPROBE_DEFER) > dev_err(dev, "Failed to get interrupt: %d\n", ret);