Re: ARMv8 != arm64

["Paul E. McKenney" <paulmck@linux.vnet.ibm.com>]

On Thu, Nov 02, 2017 at 08:22:46AM +0900, Akira Yokosawa wrote:
> On 2017/11/01 15:52:51 -0700, Paul E. McKenney wrote:
> > On Thu, Nov 02, 2017 at 07:34:28AM +0900, Akira Yokosawa wrote:
> >> Hi Paul,
> >>
> >> In Section 15.4.3, you are treating ARMv8 as 64-bit CPU.
> >> However, ARMv8 has 32-bit modes A32 and T32.
> >> Instructions for load-acquire/store-release are also available in A32
> >> and T32 modes of ARMv8.
> >>
> >> The opening paragraph of Section 15.4.3 needs some rework, I guess.
> > 
> > Ah, thank you!  How about the following?
> 
> Looks good to me!
> 
> Acked-by: Akira Yokosawa <akiyks@gmail.com>

Glad you like it, added your ack and pushed it.  ;-)

							Thanx, Paul

>     Thanks, Akira
> 
> > 
> > 							Thanx, Paul
> > 
> > ------------------------------------------------------------------------
> > 
> > commit 1a41fa1352ff77c3a09a4d182649e571735d7f1c
> > Author: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
> > Date:   Wed Nov 1 15:51:06 2017 -0700
> > 
> >     memorder: ARMv8 includes 32-bit capability
> >     
> >     Reported-by: Akira Yokosawa <akiyks@gmail.com>
> >     Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
> > 
> > diff --git a/memorder/memorder.tex b/memorder/memorder.tex
> > index 94e125ab3412..446f4804af53 100644
> > --- a/memorder/memorder.tex
> > +++ b/memorder/memorder.tex
> > @@ -4485,10 +4485,11 @@ lines~3 and~4 would enforce ordering between lines~1 and~5.
> >  \ContributedBy{Figure}{fig:memorder:Half Memory Barrier}{Melissa Brossard}
> >  \end{figure}
> >  
> > -ARMv8 is ARM's 64-bit CPU~\cite{ARMv8A:2017},
> > -in contrast to their 32-bit CPU described in
> > +ARMv8 is ARM's new CPU family~\cite{ARMv8A:2017}
> > +which includes 64-bit capabilities,
> > +in contrast to their 32-bit-only CPU described in
> >  Section~\ref{sec:memorder:ARMv7-A/R}.
> > -ARMv8's memory model closely resembles its 32-bit counterpart,
> > +ARMv8's memory model closely resembles its ARMv7 counterpart,
> >  but adds load-acquire (\co{LDLARB}, \co{LDLARH}, and \co{LDLAR})
> >  and store-release (\co{STLLRB}, \co{STLLRH}, and \co{STLLR})
> >  instructions.
> > @@ -4569,7 +4570,7 @@ being weakly ordered by default, but respecting dependencies.
> >  MIPS has a wide variety of memory-barrier instructions, but ties them
> >  not to hardware considerations, but rather to the use cases provided
> >  by the Linux kernel and the C++11 standard~\cite{RichardSmith2015N4527}
> > -in a manner similar to the ARM64 additions:
> > +in a manner similar to the ARMv8 additions:
> >  
> >  \begin{description}[style=nextline]
> >  \item[\tco{SYNC}]
> > 
> > 
>