From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Thu, 2 Nov 2017 01:12:05 -0700 From: Stephen Boyd To: sean.wang@mediatek.com Cc: mturquette@baylibre.com, robh+dt@kernel.org, matthias.bgg@gmail.com, mark.rutland@arm.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chen Zhong Subject: Re: [PATCH v2 2/4] clk: mediatek: add the option for determining PLL source clock Message-ID: <20171102081205.GG11011@codeaurora.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii In-Reply-To: List-ID: On 10/05, sean.wang@mediatek.com wrote: > From: Chen Zhong > > Since the previous setup always sets the PLL using crystal 26MHz, this > doesn't always happen in every MediaTek platform. So the patch added > flexibility for assigning extra member for determining the PLL source > clock. > > Signed-off-by: Chen Zhong > Signed-off-by: Sean Wang > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH v2 2/4] clk: mediatek: add the option for determining PLL source clock Date: Thu, 2 Nov 2017 01:12:05 -0700 Message-ID: <20171102081205.GG11011@codeaurora.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+glpam-linux-mediatek=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org, matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, Chen Zhong , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-mediatek@lists.infradead.org On 10/05, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote: > From: Chen Zhong > > Since the previous setup always sets the PLL using crystal 26MHz, this > doesn't always happen in every MediaTek platform. So the patch added > flexibility for assigning extra member for determining the PLL source > clock. > > Signed-off-by: Chen Zhong > Signed-off-by: Sean Wang > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 From: sboyd@codeaurora.org (Stephen Boyd) Date: Thu, 2 Nov 2017 01:12:05 -0700 Subject: [PATCH v2 2/4] clk: mediatek: add the option for determining PLL source clock In-Reply-To: References: Message-ID: <20171102081205.GG11011@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 10/05, sean.wang at mediatek.com wrote: > From: Chen Zhong > > Since the previous setup always sets the PLL using crystal 26MHz, this > doesn't always happen in every MediaTek platform. So the patch added > flexibility for assigning extra member for determining the PLL source > clock. > > Signed-off-by: Chen Zhong > Signed-off-by: Sean Wang > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project